soc: xtensa: Lower HW_STATE_CHECK_DELAY

The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).

1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.

2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>