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Commit 29b0cd42 authored by Francois Ramu's avatar Francois Ramu Committed by Fabio Baltieri
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drivers: clock_control: stm32h5 driver input vco range



Set the correct VCO input range for the PLL frequency
with each bit PLL1RGE of the PLL1CFGR register
This get_vco_input_range is similar to the stm32h7 one.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 154e415c
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