drivers: i3c: cdns: set tx fifo threshold interrupt to half the fifo

When a controller is running at full SDR speed at 12.5MHz, there needs
to be enough time for the processor get around to writing more data in
the fifo. Previously at -1 the size, this was enough for 1MHz with a
decent processor, but not enough at a 12.5MHz SCL.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>