drivers: i3c: cadence: fix tx_fifo width for target mode on REV_ID 1.7

Cadence I3C target FIFO width has been increased to 4 bytes in i3c
hardware REV_ID 1.7. Writing 1 byte to 4 byte FIFOs can cause
unintentional padding for bytes written from TX threshold interrupt
handler. Fixed the target callback to handle tx width of i3c target
writes to FIFO, by using run time rev_id check.

Signed-off-by: Naveen Gangadharan <naveeng1001@meta.com>