Commit 23053cfe authored by Manuel Argüelles's avatar Manuel Argüelles Committed by Anas Nashif
Browse files

boards: arm: introduce support for NXP UCANS32K1SIC



Introduce minimal support for NXP UCANS32K1SIC board based on
S32K146 MCUs. This includes support to run from internal Flash or SRAM,
multiple west runners for TRACE32 and J-Link, and the minimal set of
drivers.

Signed-off-by: default avatarManuel Argüelles <manuel.arguelles@nxp.com>
parent 81de2af6
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# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0

config BOARD_UCANS32K1SIC
	bool "ucans32k1sic"
	depends on SOC_SERIES_S32K1XX
	select SOC_PART_NUMBER_FS32K146UAT0VLHT
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# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0

if BOARD_UCANS32K1SIC

config BOARD
	default "ucans32k1sic"

if SERIAL

config UART_CONSOLE
	default y

endif # SERIAL

endif # BOARD_UCANS32K1SIC
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# Copyright 2023 NXP
# SPDX-License-Identifier: Apache-2.0

board_runner_args(jlink
  "--device=S32K146"
  "--speed=4000"
  "--iface=swd"
  "--reset"
)

board_runner_args(trace32
  "--startup-args" "elfFile=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}"
)
if(${CONFIG_XIP})
  board_runner_args(trace32 "loadTo=flash")
else()
  board_runner_args(trace32 "loadTo=sram")
endif()

include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/trace32.board.cmake)
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.. _ucans32k1sic:

NXP UCANS32K1SIC
################

Overview
********

`NXP UCANS32K1SIC`_ is a CAN signal improvement capability (SIC) evaluation
board designed for both automotive and industrial applications. The UCANS32K1SIC
provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F
`NXP S32K146`_ microcontroller.

.. image:: img/ucans32k1sic_top.webp
     :align: center
     :alt: NXP UCANS32K1SIC (TOP)

Hardware
********

- NXP S32K146
    - Arm Cortex-M4F @ up to 112 Mhz
    - 1 MB Flash
    - 128 KB SRAM
    - up to 127 I/Os
    - 3x FlexCAN with 2x FD
    - eDMA, 12-bit ADC, MPU, ECC and more.

- Interfaces:
    - DCD-LZ debug interface with SWD + Console / UART
    - Dual CAN FD PHYs with dual connectors for daisy chain operation
    - JST-GH DroneCode compliant standard connectors and I/O headers
    - user RGB LED and button.

More information about the hardware and design resources can be found at
`NXP UCANS32K1SIC`_ website.

Supported Features
==================

The ``ucans32k1sic`` board configuration supports the following hardware features:

============  ==========  ================================
Interface     Controller  Driver/Component
============  ==========  ================================
SYSMPU        on-chip     mpu
PORT          on-chip     pinctrl
GPIO          on-chip     gpio
LPUART        on-chip     serial
============  ==========  ================================

The default configuration can be found in the Kconfig file
:zephyr_file:`boards/arm/ucans32k1sic/ucans32k1sic_defconfig`.

Connections and IOs
===================

This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``.

Pin control can be further configured from your application overlay by adding
children nodes with the desired pinmux configuration to the singleton node
``pinctrl``. Supported properties are described in
:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`.

LEDs
----

The UCANS32K1SIC board has one user RGB LED:

=======================  ==============  =====
Devicetree node          Label           Pin
=======================  ==============  =====
led0 / led1_red          LED1_RGB_RED    PTD15
led1 / led1_green        LED1_RGB_GREEN  PTD16
led2 / led1_blue         LED1_RGB_BLUE   PTD0
=======================  ==============  =====

The user can control the LEDs in any way. An output of ``0`` illuminates the LED.

Buttons
-------

The UCANS32K1SIC board has one user button:

=======================  ==============  =====
Devicetree node          Label           Pin
=======================  ==============  =====
sw0 / button_3           SW3             PTD15
=======================  ==============  =====

Serial Console
==============

The serial console is provided via ``lpuart1`` on the 7-pin DCD-LZ debug
connector ``P6``.

=========  =====  ============
Connector  Pin    Pin Function
=========  =====  ============
P6.2       PTC7   LPUART1_TX
P6.3       PTC6   LPUART1_RX
=========  =====  ============

System Clock
============

The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode).

Programming and Debugging
*************************

Applications for the ``ucans32k1sic`` board can be built in the usual way as
documented in :ref:`build_an_application`.

This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_
West runners for flashing and debugging applications. Follow the steps described
in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`,
to setup the flash and debug host tools for these runners, respectively. The
default runner is J-Link.

Flashing
========

Run the ``west flash`` command to flash the application using SEGGER J-Link.
Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32.

The Lauterbach TRACE32 runner supports additional options that can be passed
through command line:

.. code-block:: console

   west flash -r trace32 --startup-args elfFile=<elf_path> loadTo=<flash/sram>
      eraseFlash=<yes/no> verifyFlash=<yes/no>

Where:

- ``<elf_path>`` is the path to the Zephyr application ELF in the output
  directory
- ``loadTo=flash`` loads the application to the SoC internal program flash
  (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the
  application to SRAM. The default is ``flash``.
- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the
  application is downloaded to either Flash or SRAM. This routine takes time to
  execute. The default is ``no``.
- ``verifyFlash=yes`` verify the SoC internal flash content after programming
  (use together with ``loadTo=flash``). The default is ``no``.

For example, to erase and verify flash content:

.. code-block:: console

   west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes

Debugging
=========

Run the ``west debug`` command to start a GDB session using SEGGER J-Link.
Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32
software debugging interface.

References
**********

.. target-notes::

.. _NXP UCANS32K1SIC:
   https://www.nxp.com/design/development-boards/analog-toolbox/can-sic-evaluation-board:UCANS32K1SIC

.. _NXP S32K146:
   https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1

.. _Lauterbach TRACE32:
   https://www.lauterbach.com

.. _SEGGER J-Link:
   https://wiki.segger.com/S32Kxxx
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