Commit 81de2af6 authored by Manuel Argüelles's avatar Manuel Argüelles Committed by Anas Nashif
Browse files

dts: arm: introduce support for NXP S32K146 



Add minimal support for S32K146 devices including clocks, MPU,
pin control, GPIO and UART.

Signed-off-by: default avatarManuel Argüelles <manuel.arguelles@nxp.com>
parent 91293187

dts/arm/nxp/nxp_s32k146.dtsi

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/*

 * Copyright 2023 NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <dt-bindings/clock/nxp_s32k146_clock.h>

#include <nxp/nxp_s32k1xx.dtsi>



/ {

	cpus {

		cpu@0 {

			compatible = "arm,cortex-m4f";

		};

	};



	soc {

		/*

		 * SRAM_L and SRAM_U ranges form a contiguous block but misaligned

		 * and burst accesses cannot occur across the 0x20000000 boundary

		 * that separates the two SRAM arrays. Hence, treat the two arrays

		 * as separate memory ranges.

		 */

		sram_l: sram@1fff0000 {

			compatible = "mmio-sram";

			reg = <0x1fff0000 DT_SIZE_K(64)>;

		};



		sram_u: sram@20000000 {

			compatible = "mmio-sram";

			reg = <0x20000000 DT_SIZE_K(60)>;

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <4>;

};



&ftfc {

	flash0: flash@0 {

		compatible = "soc-nv-flash";

		reg = <0 DT_SIZE_M(1)>;

		erase-block-size = <DT_SIZE_K(4)>;

		write-block-size = <8>;

	};

};



&lpuart2 {

	clocks = <&clock NXP_S32_LPUART2_CLK>;

};

dts/arm/nxp/nxp_s32k1xx.dtsi

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/*

 * Copyright 2023 NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <mem.h>

#include <arm/armv7-m.dtsi>



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			reg = <0>;

		};

	};



	/* Dummy pinctrl node, filled with pin mux options at board level */

	pinctrl: pinctrl {

		compatible = "nxp,kinetis-pinctrl";

		status = "okay";

	};



	soc {

		interrupt-parent = <&nvic>;



		mpu: mpu@4000d000 {

			compatible = "nxp,kinetis-mpu";

			reg = <0x4000d000 0x1000>;

			status = "disabled";

		};



		ftfc: flash-controller@40020000 {

			compatible = "nxp,kinetis-ftfc";

			reg = <0x40020000 0x1000>;

			interrupts = <18 0>, <19 0>, <21 0>;

			interrupt-names = "command-complete", "read-collision", "double-bit";

			#address-cells = <1>;

			#size-cells = <1>;

			status = "disabled";

		};



		porta: pinmux@40049000 {

			compatible = "nxp,kinetis-pinmux";

			reg = <0x40049000 0x1000>;

			clocks = <&clock NXP_S32_PORTA_CLK>;

		};



		portb: pinmux@4004a000 {

			compatible = "nxp,kinetis-pinmux";

			reg = <0x4004a000 0x1000>;

			clocks = <&clock NXP_S32_PORTB_CLK>;

		};



		portc: pinmux@4004b000 {

			compatible = "nxp,kinetis-pinmux";

			reg = <0x4004b000 0x1000>;

			clocks = <&clock NXP_S32_PORTC_CLK>;

		};



		portd: pinmux@4004c000 {

			compatible = "nxp,kinetis-pinmux";

			reg = <0x4004c000 0x1000>;

			clocks = <&clock NXP_S32_PORTD_CLK>;

		};



		porte: pinmux@4004d000 {

			compatible = "nxp,kinetis-pinmux";

			reg = <0x4004d000 0x1000>;

			clocks = <&clock NXP_S32_PORTE_CLK>;

		};



		clock: clock-controller@40064000 {

			compatible = "nxp,s32-clock";

			reg = <0x40064000 0x1000>, <0x40065000 0x1000>;

			#clock-cells = <1>;

			status = "okay";

		};



		lpuart0: uart@4006a000 {

			compatible = "nxp,kinetis-lpuart";

			reg = <0x4006a000 0x1000>;

			interrupts = <31 0>;

			clocks = <&clock NXP_S32_LPUART0_CLK>;

			status = "disabled";

		};



		lpuart1: uart@4006b000 {

			compatible = "nxp,kinetis-lpuart";

			reg = <0x4006b000 0x1000>;

			interrupts = <33 0>;

			clocks = <&clock NXP_S32_LPUART1_CLK>;

			status = "disabled";

		};



		lpuart2: uart@4006c000 {

			compatible = "nxp,kinetis-lpuart";

			reg = <0x4006c000 0x1000>;

			interrupts = <35 0>;

			status = "disabled";

		};



		gpioa: gpio@400ff000 {

			compatible = "nxp,kinetis-gpio";

			reg = <0x400ff000 0x40>;

			interrupts = <59 2>;

			gpio-controller;

			#gpio-cells = <2>;

			nxp,kinetis-port = <&porta>;

			status = "disabled";

		};



		gpiob: gpio@400ff040 {

			compatible = "nxp,kinetis-gpio";

			reg = <0x400ff040 0x40>;

			interrupts = <60 2>;

			gpio-controller;

			#gpio-cells = <2>;

			nxp,kinetis-port = <&portb>;

			status = "disabled";

		};



		gpioc: gpio@400ff080 {

			compatible = "nxp,kinetis-gpio";

			reg = <0x400ff080 0x40>;

			interrupts = <61 2>;

			gpio-controller;

			#gpio-cells = <2>;

			nxp,kinetis-port = <&portc>;

			status = "disabled";

		};



		gpiod: gpio@400ff0c0 {

			compatible = "nxp,kinetis-gpio";

			reg = <0x400ff0c0 0x40>;

			interrupts = <62 2>;

			gpio-controller;

			#gpio-cells = <2>;

			nxp,kinetis-port = <&portd>;

			status = "disabled";

		};



		gpioe: gpio@400ff100 {

			compatible = "nxp,kinetis-gpio";

			reg = <0x400ff100 0x40>;

			interrupts = <63 2>;

			gpio-controller;

			#gpio-cells = <2>;

			nxp,kinetis-port = <&porte>;

			status = "disabled";

		};

	};

};

include/zephyr/dt-bindings/clock/nxp_s32k146_clock.h

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/*

 * Copyright 2023 NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_

#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_



#define NXP_S32_LPO_128K_CLK                       1U

#define NXP_S32_SIRC_CLK                           2U

#define NXP_S32_SIRC_VLP_CLK                       3U

#define NXP_S32_SIRC_STOP_CLK                      4U

#define NXP_S32_FIRC_CLK                           5U

#define NXP_S32_FIRC_VLP_CLK                       6U

#define NXP_S32_FIRC_STOP_CLK                      7U

#define NXP_S32_SOSC_CLK                           8U

#define NXP_S32_SPLL_CLK                           9U

#define NXP_S32_SIRCDIV1_CLK                       10U

#define NXP_S32_SIRCDIV2_CLK                       11U

#define NXP_S32_FIRCDIV1_CLK                       12U

#define NXP_S32_FIRCDIV2_CLK                       13U

#define NXP_S32_SOSCDIV1_CLK                       14U

#define NXP_S32_SOSCDIV2_CLK                       15U

#define NXP_S32_SPLLDIV1_CLK                       16U

#define NXP_S32_SPLLDIV2_CLK                       17U

#define NXP_S32_LPO_32K_CLK                        18U

#define NXP_S32_LPO_1K_CLK                         19U

#define NXP_S32_TCLK0_REF_CLK                      20U

#define NXP_S32_TCLK1_REF_CLK                      21U

#define NXP_S32_TCLK2_REF_CLK                      22U

#define NXP_S32_SCS_CLK                            24U

#define NXP_S32_SCS_RUN_CLK                        25U

#define NXP_S32_SCS_VLPR_CLK                       26U

#define NXP_S32_SCS_HSRUN_CLK                      27U

#define NXP_S32_CORE_CLK                           28U

#define NXP_S32_CORE_RUN_CLK                       29U

#define NXP_S32_CORE_VLPR_CLK                      30U

#define NXP_S32_CORE_HSRUN_CLK                     31U

#define NXP_S32_BUS_CLK                            32U

#define NXP_S32_BUS_RUN_CLK                        33U

#define NXP_S32_BUS_VLPR_CLK                       34U

#define NXP_S32_BUS_HSRUN_CLK                      35U

#define NXP_S32_SLOW_CLK                           36U

#define NXP_S32_SLOW_RUN_CLK                       37U

#define NXP_S32_SLOW_VLPR_CLK                      38U

#define NXP_S32_SLOW_HSRUN_CLK                     39U

#define NXP_S32_RTC_CLK                            40U

#define NXP_S32_LPO_CLK                            41U

#define NXP_S32_SCG_CLKOUT_CLK                     42U

#define NXP_S32_FTM0_EXT_CLK                       43U

#define NXP_S32_FTM1_EXT_CLK                       44U

#define NXP_S32_FTM2_EXT_CLK                       45U

#define NXP_S32_FTM3_EXT_CLK                       46U

#define NXP_S32_FTM4_EXT_CLK                       47U

#define NXP_S32_FTM5_EXT_CLK                       48U

#define NXP_S32_ADC0_CLK                           50U

#define NXP_S32_ADC1_CLK                           51U

#define NXP_S32_CLKOUT0_CLK                        52U

#define NXP_S32_CMP0_CLK                           53U

#define NXP_S32_CRC0_CLK                           54U

#define NXP_S32_DMA0_CLK                           55U

#define NXP_S32_DMAMUX0_CLK                        56U

#define NXP_S32_EIM0_CLK                           57U

#define NXP_S32_ERM0_CLK                           58U

#define NXP_S32_EWM0_CLK                           59U

#define NXP_S32_FLEXCAN0_CLK                       60U

#define NXP_S32_FLEXCAN1_CLK                       61U

#define NXP_S32_FLEXCAN2_CLK                       62U

#define NXP_S32_FLEXIO_CLK                         63U

#define NXP_S32_FTFC_CLK                           64U

#define NXP_S32_FTM0_CLK                           65U

#define NXP_S32_FTM1_CLK                           66U

#define NXP_S32_FTM2_CLK                           67U

#define NXP_S32_FTM3_CLK                           68U

#define NXP_S32_FTM4_CLK                           69U

#define NXP_S32_FTM5_CLK                           70U

#define NXP_S32_LPI2C0_CLK                         71U

#define NXP_S32_LPIT0_CLK                          72U

#define NXP_S32_LPSPI0_CLK                         73U

#define NXP_S32_LPSPI1_CLK                         74U

#define NXP_S32_LPSPI2_CLK                         75U

#define NXP_S32_LPTMR0_CLK                         76U

#define NXP_S32_LPUART0_CLK                        77U

#define NXP_S32_LPUART1_CLK                        78U

#define NXP_S32_LPUART2_CLK                        79U

#define NXP_S32_MPU0_CLK                           80U

#define NXP_S32_MSCM0_CLK                          81U

#define NXP_S32_PDB0_CLK                           82U

#define NXP_S32_PDB1_CLK                           83U

#define NXP_S32_PORTA_CLK                          84U

#define NXP_S32_PORTB_CLK                          85U

#define NXP_S32_PORTC_CLK                          86U

#define NXP_S32_PORTD_CLK                          87U

#define NXP_S32_PORTE_CLK                          88U

#define NXP_S32_RTC0_CLK                           89U

#define NXP_S32_TRACE_CLK                          90U



#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_ */

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