logging: backends: Use CMSIS 6 register defines in SWO initialization

ARM CMSIS 6 has different ITM and TPI register definition comparing
with CMSIS 5. Update the swo initialization to use CMSIS 6 defines.
For the Cortex-M cores which are higher than Cortex-CM7, the LAR
has been removed from ITM.

Signed-off-by: Aaron Ye <aye@ambiq.com>