dts: riscv: Add aesc (2120b82e) · Commits · Wenxi XU / zephyr

dts/riscv/aesc/elemrv-n.dtsi

0 → 100644

+25 −0

Changes for dts/riscv/aesc/elemrv-n.dtsi: 25 added lines, 0 removed lines.
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		/*
		* Copyright (c) 2025 Aesc Silicon
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <aesc/nitrogen.dtsi>

		/ {
		#address-cells = <1>;
		#size-cells = <1>;

		soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "aesc,elemrv-n-soc", "simple-bus";
		ranges;

		uart0: uart0@f0006000 {
		compatible = "aesc,uart";
		reg = <0xf0006000 0x1000>;
		status = "disabled";
		};
		};
		};

0 → 100644

+48 −0

Changes for dts/riscv/aesc/nitrogen.dtsi: 48 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2025 Aesc Silicon
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <zephyr/dt-bindings/gpio/gpio.h>
		#include <freq.h>
		#include <mem.h>

		/ {
		#address-cells = <1>;
		#size-cells = <1>;

		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
		compatible = "litex,vexriscv-standard";
		device_type = "cpu";
		reg = <0>;
		riscv,isa = "rv32imc";
		status = "okay";

		hlic: interrupt-controller {
		compatible = "riscv,cpu-intc";
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		};
		};
		};

		soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "aesc,nitrogen-soc", "simple-bus";
		ranges;

		mtimer: machine-timer@f0020000 {
		compatible = "riscv,machine-timer";
		reg = <0xf0020000 0x8 0xf0020008 0x8>;
		interrupts-extended = <&hlic 7>;
		status = "okay";
		};
		};
		};