soc: common: riscv-privileged: align to no SW ISR table (1d9907a7) · Commits · Wenxi XU / zephyr

In case of no SW ISR table, `_isr_wrapper` does not exist. Do not use it for exception handling. Future improvements might include setting it to a user-defined handler. Signed-off-by:

Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>

soc/common/riscv-privileged/vector.S

+6 −0

Original line number	Diff line number	Diff line
		@@ -12,7 +12,9 @@ GTEXT(__start)

		/* imports */
		GTEXT(__initialize)
		#if defined(CONFIG_GEN_SW_ISR_TABLE)
		GTEXT(_isr_wrapper)
		#endif

		SECTION_FUNC(vectors, __start)
		#if defined(CONFIG_RISCV_GP)
		@@ -35,7 +37,11 @@ SECTION_FUNC(vectors, __start)
		* mtvec.base must be aligned to 64 bytes (this is done using
		* CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
		*/
		#if defined(CONFIG_GEN_SW_ISR_TABLE)
		la t0, _isr_wrapper
		#else
		add t0, zero, zero
		#endif
		addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
		csrw mtvec, t0

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