Commit 1b931af0 authored by Peter Marheine's avatar Peter Marheine Committed by Carles Cufi
Browse files

it8xxx2: fix build with CONFIG_SOC_IT8XXX2_PLL_FLASH_48M=n 



The chip I2C driver uses chip_get_pll_freq(), so that function needs to
be built even when the PLL configuration is not changed at boot.

Signed-off-by: default avatarPeter Marheine <pmarheine@chromium.org>
parent 0422a04b

soc/riscv/riscv-ite/it8xxx2/soc.c

+36 −36
Original line number Diff line number Diff line
@@ -13,42 +13,6 @@ 
#include "soc_espi.h"

#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>



#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M



struct pll_config_t {

	uint8_t pll_freq;

	uint8_t div_fnd;

	uint8_t div_uart;

	uint8_t div_smb;

	uint8_t div_sspi;

	uint8_t div_ec;

	uint8_t div_jtag;

	uint8_t div_pwm;

	uint8_t div_usbpd;

};



static const struct pll_config_t pll_configuration[] = {

	/*

	 * PLL frequency setting = 4 (48MHz)

	 * FND   div = 0 (PLL / 1 = 48 mhz)

	 * UART  div = 1 (PLL / 2 = 24 mhz)

	 * SMB   div = 1 (PLL / 2 = 24 mhz)

	 * SSPI  div = 1 (PLL / 2 = 24 mhz)

	 * EC    div = 6 (FND / 6 =  8 mhz)

	 * JTAG  div = 1 (PLL / 2 = 24 mhz)

	 * PWM   div = 0 (PLL / 1 = 48 mhz)

	 * USBPD div = 5 (PLL / 6 =  8 mhz)

	 */

	{.pll_freq  = 4,

	 .div_fnd   = 0,

	 .div_uart  = 1,

	 .div_smb   = 1,

	 .div_sspi  = 1,

	 .div_ec    = 6,

	 .div_jtag  = 1,

	 .div_pwm   = 0,

	 .div_usbpd = 5}

};



uint32_t chip_get_pll_freq(void)

{
@@ -99,6 +63,42 @@ void __soc_ram_code chip_pll_ctrl(enum chip_pll_mode mode) 
	_pll_ctrl = IT8XXX2_ECPM_PLLCTRL;

}



#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M

struct pll_config_t {

	uint8_t pll_freq;

	uint8_t div_fnd;

	uint8_t div_uart;

	uint8_t div_smb;

	uint8_t div_sspi;

	uint8_t div_ec;

	uint8_t div_jtag;

	uint8_t div_pwm;

	uint8_t div_usbpd;

};



static const struct pll_config_t pll_configuration[] = {

	/*

	 * PLL frequency setting = 4 (48MHz)

	 * FND   div = 0 (PLL / 1 = 48 mhz)

	 * UART  div = 1 (PLL / 2 = 24 mhz)

	 * SMB   div = 1 (PLL / 2 = 24 mhz)

	 * SSPI  div = 1 (PLL / 2 = 24 mhz)

	 * EC    div = 6 (FND / 6 =  8 mhz)

	 * JTAG  div = 1 (PLL / 2 = 24 mhz)

	 * PWM   div = 0 (PLL / 1 = 48 mhz)

	 * USBPD div = 5 (PLL / 6 =  8 mhz)

	 */

	{.pll_freq  = 4,

	 .div_fnd   = 0,

	 .div_uart  = 1,

	 .div_smb   = 1,

	 .div_sspi  = 1,

	 .div_ec    = 6,

	 .div_jtag  = 1,

	 .div_pwm   = 0,

	 .div_usbpd = 5}

};



void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll)

{

	/* Enable HW timer to wakeup chip from the sleep mode */

CRA Git | Maintained and supported by SUSTech CRA and CCSE