soc/intel_adsp: Rework Xtensa region protection initialization

Our "TLB"[1] initialization on secondary cores for cAVS 2.5 was
forgetting to initialize instruction caching, leading to a performance
regression.  Clean this up and augment so that it matches the (larger,
non-C-callable) HAL implementation.

This will also allow us to use the same code on the main core in
upcoming changes.

[1] It's not a TLB, it just uses the TLB management instructions

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>