boards: arm: nucleo_f746zg change the sysclock for can timings

Because of CAN bus clock, some bitrate values might not not give
a valid timing calculation depending on the CAN bus freq.
The sysclock is changed to the highest common value between
USB 48MHz and CAN.
The result is a sysclock of 192MHz. Then is USB at 48MHz
and the CAN bus freq is the APB1 (PCLK1) at 48MHz

Signed-off-by: Francois Ramu <francois.ramu@st.com>