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Commit 175407c9 authored by Naveen Gangadharan's avatar Naveen Gangadharan Committed by Carles Cufí
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drivers: i3c: cadence: fix HDR-DDR write failures due to M1 errors 



Fix M1 errors seen with HDR-DDR writes, M1 errors we seen between CRC
and HDR exit sequence. The fix was to set Bit-8 of HDR-DDR CRC TXFIFO
word.

Signed-off-by: default avatarNaveen Gangadharan <naveeng1001@meta.com>
parent e48639e4
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