Commit 16e74b92 authored by Declan Snyder's avatar Declan Snyder Committed by Daniel DeGrasse
Browse files

soc: imxrt: Clean up INIT_ARM_PLL config 



Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.

The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.

And of course, code for this was a mess, clean up a bit.

Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.

Signed-off-by: default avatarDeclan Snyder <declan.snyder@nxp.com>
parent d33f7feb

soc/nxp/imxrt/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -179,6 +179,9 @@ config DCDC_VALUE 
	hex "DCDC value for VDD_SOC"



config INIT_ARM_PLL

	default y

	depends on !SOC_MIMXRT1011 && !SOC_MIMXRT1015 && \

		   !SOC_MIMXRT1021 && !SOC_MIMXRT1024

	bool "Initialize ARM PLL"



config INIT_VIDEO_PLL

soc/nxp/imxrt/imxrt10xx/Kconfig

+0 −4
Original line number Diff line number Diff line
@@ -65,7 +65,6 @@ config SOC_MIMXRT1042 
	select HAS_MCUX_SEMC

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_SYS_PLL



config SOC_MIMXRT1052
@@ -74,7 +73,6 @@ config SOC_MIMXRT1052 
	select HAS_MCUX_SEMC

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2
@@ -91,7 +89,6 @@ config SOC_MIMXRT1062 
	select HAS_MCUX_SNVS

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2
@@ -110,7 +107,6 @@ config SOC_MIMXRT1064 
	select HAS_MCUX_SRC

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

soc/nxp/imxrt/imxrt10xx/soc.c

+4 −7
Original line number Diff line number Diff line
@@ -33,13 +33,6 @@ 
		     DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \

		     #podf " is out of supported range (" #a ", " #b ")")



#ifdef CONFIG_INIT_ARM_PLL

/* ARM PLL configuration for RUN mode */

const clock_arm_pll_config_t armPllConfig = {

	.loopDivider = 100U

};

#endif



#if CONFIG_INIT_SYS_PLL

/* Configure System PLL */

const clock_sys_pll_config_t sysPllConfig = {
@@ -132,6 +125,10 @@ __weak void clock_init(void) 
#endif



#ifdef CONFIG_INIT_ARM_PLL

	/* ARM PLL configuration for RUN mode */

	static const clock_arm_pll_config_t armPllConfig = {

		.loopDivider = 100U

	};

	CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */

#endif

soc/nxp/imxrt/imxrt118x/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ config SOC_SERIES_IMXRT118X 
	select CPU_HAS_ARM_MPU

	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS

	select ARM_MPU

	select INIT_ARM_PLL

	select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33

	select CPU_HAS_ICACHE

	select CPU_HAS_DCACHE

soc/nxp/imxrt/imxrt11xx/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ config SOC_SERIES_IMXRT11XX 
	select HAS_MCUX_FLEXSPI

	select HAS_MCUX_FLEXCAN

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL

	select HAS_MCUX_EDMA

	select CPU_HAS_ICACHE if CPU_CORTEX_M7

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