Commit d33f7feb authored by Declan Snyder's avatar Declan Snyder Committed by Daniel DeGrasse
Browse files

soc: imxrt: Clean up INIT_ENET_PLL config 



Initial motivation for this commit was to not force select
the INIT_ENET_PLL config from SOC level to allow for board level
configuration which might want it to be off.

While doing that, I discovered that RT11xx actually does not have
anything called by "ENET PLL" in the reference manual. So I have
removed the config for RT11xx. The default clock source for this soc.c
code for RT11xx is PLL1 DIV2, which I changed to just be configured if
ethernet is enabled, which was the reason to configure this pll as it
stands now, even though it is not specific to ethernet (although the
DIV2 output is mostly for ethernet). Another config is therefore not
needed.

For RT10xx, the situation is a lot more complicated. There is a lot of
discrepancy again between what is considered the "ENET PLL" both
conceptually and literally between the RM, SDK, and Zephyr config. And
also the code to define the config struct was a complete mess. So I have
simplified the code and changed it so that the config is only a soft
default to y instead of selected forcefully. Also, for the case of the
RT1010 and RT1020 series, the SDK is appearing to configure PLL6 (again
there is no clear ENET PLL meaning on these platforms) 500M output
through this "enet pll" configuration function. So similarly instead of
always enabling this output for those platforms, I added a new config
which can be set or unset by board level.

Signed-off-by: default avatarDeclan Snyder <declan.snyder@nxp.com>
parent f775f9a9

soc/nxp/imxrt/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -184,13 +184,6 @@ config INIT_ARM_PLL 
config INIT_VIDEO_PLL

	bool "Initialize Video PLL"



config INIT_ENET_PLL

	bool

	help

	  If y, the Ethernet PLL is initialized. Always enabled on e.g.

	  MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection

	  for MIMXRT1021").



config INIT_SYS_PLL

	bool "Initialize System PLL"

soc/nxp/imxrt/imxrt10xx/Kconfig

+21 −7
Original line number Diff line number Diff line
@@ -35,20 +35,17 @@ config SOC_MIMXRT1011 
	select CPU_HAS_ARM_MPU

	select CPU_HAS_ICACHE

	select CPU_HAS_DCACHE

	select INIT_ENET_PLL



config SOC_MIMXRT1015

	select CPU_HAS_FPU

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ENET_PLL



config SOC_MIMXRT1021

	select HAS_MCUX_ENET

	select HAS_MCUX_SEMC

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ENET_PLL

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

	select HAS_MCUX_FLEXCAN
@@ -59,7 +56,6 @@ config SOC_MIMXRT1024 
	select HAS_MCUX_SEMC

	select CPU_HAS_FPU_DOUBLE_PRECISION

	select CPU_HAS_ARM_MPU

	select INIT_ENET_PLL

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

	select HAS_MCUX_FLEXCAN
@@ -80,7 +76,6 @@ config SOC_MIMXRT1052 
	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

	select HAS_MCUX_FLEXCAN
@@ -98,7 +93,6 @@ config SOC_MIMXRT1062 
	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

	select HAS_MCUX_FLEXCAN
@@ -118,8 +112,28 @@ config SOC_MIMXRT1064 
	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF

	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2

	select HAS_MCUX_FLEXCAN

	select HAS_SWO



if SOC_SERIES_IMXRT10XX



config INIT_ENET_PLL

	bool "Initialize ENET PLL"

	default y if ETH_NXP_ENET

	help

	  When enabled, will call the SDK function to initialize the enet pll.

	  The exact meaning of what the "enet pll" is in the hardware according

	  to the SDK changes per platform, and so does the API signature.

	  This configuration also assumes a certain default clocking scheme for each SOC.

	  See soc.c code and HAL fsl_clock.c for the platform for better understanding.



config INIT_PLL6_500M

	bool "PLL6 500M output enable"

	default y

	depends on SOC_MIMXRT1011 || SOC_MIMXRT1015 || \

		   SOC_MIMXRT1021 || SOC_MIMXRT1024

	select INIT_ENET_PLL



endif # SOC_SERIES_IMXRT10XX

soc/nxp/imxrt/imxrt10xx/soc.c

+19 −32
Original line number Diff line number Diff line
@@ -57,36 +57,6 @@ const clock_sys_pll_config_t sysPllConfig = { 
#define BOARD_USB_PHY_TXCAL45DM (0x06U)

#endif



#ifdef CONFIG_INIT_ENET_PLL

/* ENET PLL configuration for RUN mode */

const clock_enet_pll_config_t ethPllConfig = {

#if defined(CONFIG_SOC_MIMXRT1011) || \

	defined(CONFIG_SOC_MIMXRT1015) || \

	defined(CONFIG_SOC_MIMXRT1021) || \

	defined(CONFIG_SOC_MIMXRT1024)

	.enableClkOutput500M = true,

#endif

#if defined(CONFIG_ETH_NXP_ENET)

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))

	.enableClkOutput = true,

#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2))

	.enableClkOutput1 = true,

#endif

#endif

#if defined(CONFIG_PTP_CLOCK_NXP_ENET)

	.enableClkOutput25M = true,

#else

	.enableClkOutput25M = false,

#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))

	.loopDivider = 1,

#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2))

	.loopDivider1 = 1,

#endif

};

#endif



#if CONFIG_USB_DC_NXP_EHCI

	usb_phy_config_struct_t usbPhyConfig = {
@@ -164,9 +134,26 @@ __weak void clock_init(void) 
#ifdef CONFIG_INIT_ARM_PLL

	CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */

#endif

#ifdef CONFIG_INIT_ENET_PLL

	CLOCK_InitEnetPll(&ethPllConfig);



	static const clock_enet_pll_config_t ethPllConfig = {

		.enableClkOutput25M = IS_ENABLED(CONFIG_PTP_CLOCK_NXP_ENET),

		.enableClkOutput = DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)),

		.loopDivider = DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)),

#if DT_NODE_EXISTS(DT_NODELABEL(enet2))

		/* some platform don't have enet 2 and sdk doesn't have these fields for it */

		.enableClkOutput1 = DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2)),

		.loopDivider1 = DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2)),

#endif

#if IS_ENABLED(CONFIG_INIT_PLL6_500M)

		/* this field only exists on some platforms, so ifdef is needed */

		.enableClkOutput500M = true,

#endif

	};



	if (IS_ENABLED(CONFIG_INIT_ENET_PLL)) {

		CLOCK_InitEnetPll(&ethPllConfig);

	}



#ifdef CONFIG_INIT_VIDEO_PLL

	CLOCK_InitVideoPll(&videoPllConfig);

#endif

soc/nxp/imxrt/imxrt11xx/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ config SOC_SERIES_IMXRT11XX 
	select HAS_MCUX_FLEXCAN

	select CPU_HAS_ARM_MPU

	select INIT_ARM_PLL

	select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER

	select INIT_VIDEO_PLL

	select HAS_MCUX_EDMA

	select CPU_HAS_ICACHE if CPU_CORTEX_M7

soc/nxp/imxrt/imxrt11xx/soc.c

+11 −17
Original line number Diff line number Diff line
@@ -90,12 +90,6 @@ static const clock_sys_pll2_config_t sysPll2Config = { 
	.ssEnable = false,

};



#ifdef CONFIG_INIT_ENET_PLL

static const clock_sys_pll1_config_t sysPll1Config = {

	.pllDiv2En = true,

};

#endif



#ifdef CONFIG_INIT_VIDEO_PLL

static const clock_video_pll_config_t videoPllConfig = {

	/* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
@@ -261,17 +255,17 @@ __weak void clock_init(void) 
	CLOCK_InitArmPll(&armPllConfig);

#endif



#ifdef CONFIG_INIT_ENET_PLL

	if (IS_ENABLED(CONFIG_ETH_NXP_ENET)) {

		/* For default clocking, we will only use pll1 for div2 output for enet */

		static const clock_sys_pll1_config_t sysPll1Config = {

			.pllDiv2En = true,

		};

		CLOCK_InitSysPll1(&sysPll1Config);

#else

#ifndef CONFIG_SECOND_CORE_MCUX

	/* Bypass Sys Pll1. */

	} else if (!IS_ENABLED(CONFIG_SECOND_CORE_MCUX)) {

		/* PLL1 not used otherwise, so bypass first then deinit */

		CLOCK_SetPllBypass(kCLOCK_PllSys1, true);



	/* DeInit Sys Pll1. */

		CLOCK_DeinitSysPll1();

#endif

#endif

	}



	/* Init Sys Pll2. */

	CLOCK_InitSysPll2(&sysPll2Config);

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