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Commit 164e4b6f authored by Dawid Niedzwiecki's avatar Dawid Niedzwiecki Committed by Carles Cufí
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clock_control: stm32f4: add PLLR division factor 



Some STM32F4xx chips have an R division factor in PLL. Add possibility
to configure that.

Even though the output from the R division is not used, it can be
increased to reduce power consumption.

Signed-off-by: default avatarDawid Niedzwiecki <dawidn@google.com>
parent 23072284
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