drivers: clock control: stm32F412 has PLL48MHz

Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
 the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.

Signed-off-by: Francois Ramu <francois.ramu@st.com>