soc/intel_adsp: Clean up cache handling in MP startup

There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.

Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).

Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>