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drivers: mdio_nxp_enet_qos: fix CR overwrite
Current Implementation to write to MAC_MDIO_ADDRESS causes CR to be
set to 0. This leads to the divide always being 42 (on FRDM_MCXN947)
so, by default the clock is running at ~3.6MHz which is out of spec
range (1.0-2.5MHz)
This stops the do_transaction function from overwriting CR.
It also saves off the CR register before DMA reset
Signed-off-by:
Jacob Wienecke <jacob.wienecke@nxp.com>