dts: psoc6: Use valid IRQ prio levels for CM4

The psoc6 SoC has 2 cores, each with different allowed priority ranges:

CM0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel)
CM4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel)

Since some of the peripherals are only available to the CM4, those
should be set to a priority that is actually valid for it. In this case
the lowest possible one is 6, so transition from 7 to 6.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>