Commit 0a9d6b84 authored by Ayush Singh's avatar Ayush Singh Committed by Henrik Brix Andersen
Browse files

dts: arm: ti: Unify I-RAM and D-RAM 

The MCU_M4FSS has a total of 256KB of SRAM divided into two banks: 192KB
of I-RAM, and 64KB of D-RAM. The I-RAM memory is intended mainly for M4F’s
instruction code, and D-RAM for M4F’s data. The M4F allows
concurrent fetch for instruction code and data via dedicated buses (I-Code
and D-Code, respectively).

The MCU_M4FSS supports unified memory for both banks (I-RAM and D-RAM),
which means instruction code and data can be placed in any bank. Since CM4
converts unaligned accesses into word-aligned accesses internally, cross
RAM access also work fine in unified memory mode.

By having a single parent node for SRAM, we allow both operating modes,
i.e. separate I-RAM and D-RAM and unified SRAM easily.

Also fixed the incorrect D-RAM address.

Signed-off-by: default avatarAyush Singh <ayush@beagleboard.org>
parent 8fd366e2

boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml

+1 −1
Changes for boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml: 1 added line, 1 removed line.
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ type: mcu 
arch: arm

toolchain:

  - zephyr

ram: 192

ram: 256

vendor: beagle

supported:

  - uart

boards/beagle/pocketbeagle_2/pocketbeagle_2_am6254_m4.yaml

+1 −1
Changes for boards/beagle/pocketbeagle_2/pocketbeagle_2_am6254_m4.yaml: 1 added line, 1 removed line.
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ type: mcu 
arch: arm

toolchain:

  - zephyr

ram: 192

ram: 256

vendor: beagle

supported:

  - uart

boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.yaml

+1 −1
Changes for boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.yaml: 1 added line, 1 removed line.
Original line number Diff line number Diff line
@@ -4,5 +4,5 @@ type: mcu 
arch: arm

toolchain:

  - zephyr

ram: 192

ram: 256

vendor: phytec

boards/ti/sk_am62/sk_am62_am6234_m4.yaml

+1 −1
Changes for boards/ti/sk_am62/sk_am62_am6234_m4.yaml: 1 added line, 1 removed line.
Original line number Diff line number Diff line
@@ -4,5 +4,5 @@ type: mcu 
arch: arm

toolchain:

  - zephyr

ram: 192

ram: 256

vendor: ti

dts/arm/ti/am62x_m4.dtsi

+20 −4
Changes for dts/arm/ti/am62x_m4.dtsi: 20 added lines, 4 removed lines.
Original line number Diff line number Diff line
@@ -24,14 +24,30 @@ 
		};

	};



	/*

	 * I-RAM and D-RAM can be used in unified mode, i.e. instruction code and data can be placed

	 * in any bank. Since unaligned accesses are converted internally by the CM4 into

	 * aligned accesses of smaller sizes, even accessing unaligned data at the boundary

	 * between I-RAM and D-RAM should not cause problems in unified mode. However, note

	 * that using unified mode can have a performance penalty.

	 */

	sram0: memory@0 {

		compatible = "mmio-sram";

		reg = <0x0 DT_SIZE_K(192)>;		/* 192 KB of SRAM (I-Code) */

		reg = <0x0 DT_SIZE_K(256)>;

		#address-cells = <0x1>;

		#size-cells = <0x1>;



		/* 192 KB of SRAM (I-Code) */

		sram_icode: memory@0 {

			device_type = "memory";

			reg = <0x00000000 DT_SIZE_K(192)>;

		};



	sram1: memory1@40000 {

		compatible = "mmio-sram";

		reg = <0x40000 DT_SIZE_K(64)>;		/* 64 KB of SRAM (D-Code) */

		/* 64 KB of SRAM (D-Code) */

		sram_dcode: memory@30000 {

			device_type = "memory";

			reg = <0x00030000 DT_SIZE_K(64)>;

		};

	};



	sysclk: system-clock {

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