dts: arm: ti: Unify I-RAM and D-RAM

The MCU_M4FSS has a total of 256KB of SRAM divided into two banks: 192KB
of I-RAM, and 64KB of D-RAM. The I-RAM memory is intended mainly for M4F’s
instruction code, and D-RAM for M4F’s data. The M4F allows
concurrent fetch for instruction code and data via dedicated buses (I-Code
and D-Code, respectively).

The MCU_M4FSS supports unified memory for both banks (I-RAM and D-RAM),
which means instruction code and data can be placed in any bank. Since CM4
converts unaligned accesses into word-aligned accesses internally, cross
RAM access also work fine in unified memory mode.

By having a single parent node for SRAM, we allow both operating modes,
i.e. separate I-RAM and D-RAM and unified SRAM easily.

Also fixed the incorrect D-RAM address.

Signed-off-by: Ayush Singh <ayush@beagleboard.org>