soc: nxp: imxrt: fix PDRV field setting for drive strength

In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding

Note that for PDRV type pins, this commit effectively switches their
drive strength setting.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>