Commit 8150ce6b authored by Guillaume Gautier's avatar Guillaume Gautier Committed by Erwan Gouriou
Browse files

lib/stm32: update stm32wb to cube version V1.16.0 

Update Cube version for STM32WBxx series
on https://github.com/STMicroelectronics
from version v1.14.0
to version v1.16.0

Signed-off-by: default avatarGuillaume Gautier <guillaume.gautier-ext@st.com>
parent 0d73e189

lib/CMakeLists.txt

+3 −3
Changes for lib/CMakeLists.txt: 3 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -8,12 +8,12 @@ if(CONFIG_HAS_STM32LIB) 
  if(CONFIG_BT_STM32_IPM)

    zephyr_include_directories(stm32wb/hci)



    zephyr_sources(stm32wb/hci/tl_mbox.c)

    zephyr_sources(stm32wb/hci/hw_ipcc.c)

    zephyr_sources(stm32wb/hci/shci_tl_if.c)

    zephyr_sources(stm32wb/hci/shci_tl.c)

    zephyr_sources(stm32wb/hci/shci.c)

    zephyr_sources(stm32wb/hci/shci_tl.c)

    zephyr_sources(stm32wb/hci/shci_tl_if.c)

    zephyr_sources(stm32wb/hci/stm_list.c)

    zephyr_sources(stm32wb/hci/tl_mbox.c)



  endif()

endif()
 
 No newline at end of file

lib/stm32wb/hci/README

+2 −2
Changes for lib/stm32wb/hci/README: 2 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   https://github.com/STMicroelectronics/STM32CubeWB



Status:

   version v1.14.0

   version v1.16.0



Purpose:

   This library is used on stm32wb series to enable HCI communication between
@@ -48,7 +48,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeWB



commit:

   83aacadecbd5136ad3194f39e002ff50a5439ad9

   2234d9783a661bd25dd626810b6a8cc7e58f7df2



Maintained-by:

   External

lib/stm32wb/hci/app_conf.h

+51 −6
Changes for lib/stm32wb/hci/app_conf.h: 51 added lines, 6 removed lines.
Original line number Diff line number Diff line
@@ -43,7 +43,19 @@ 
 * Define Advertising parameters

 */

#define CFG_ADV_BD_ADDRESS                (0x7257acd87a6c)

#define CFG_BLE_ADDRESS_TYPE              PUBLIC_ADDR /**< Bluetooth address types defined in ble_legacy.h */



/* BD_ADDR type: define proper address. Can only be GAP_PUBLIC_ADDR (0x00) or GAP_STATIC_RANDOM_ADDR (0x01) */

#define CFG_IDENTITY_ADDRESS           GAP_PUBLIC_ADDR   /* GAP_STATIC_RANDOM_ADDR */

//#define CFG_STATIC_RANDOM_ADDRESS               (0x1234567890ab) /**< Static Random Address fixed for lifetime of the device */



/* Define privacy: PRIVACY_DISABLED or PRIVACY_ENABLED */

#define CFG_PRIVACY                       PRIVACY_DISABLED /* PRIVACY_ENABLED */



/* if CFG_PRIVACY equals PRIVACY_DISABLED,  CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_PUBLIC_ADDR or GAP_STATIC_RANDOM_ADDR */

#define CFG_BLE_ADDRESS_TYPE              CFG_IDENTITY_ADDRESS /**< Bluetooth address types defined in ble_legacy.h */



/* if CFG_PRIVACY equals PRIVACY_ENABLED, CFG_BLE_ADDRESS_TYPE has 2 allowed values: GAP_RESOLVABLE_PRIVATE_ADDR or GAP_NON_RESOLVABLE_PRIVATE_ADDR */

//#define CFG_BLE_ADDRESS_TYPE              GAP_RESOLVABLE_PRIVATE_ADDR /* GAP_NON_RESOLVABLE_PRIVATE_ADDR */



#define CFG_FAST_CONN_ADV_INTERVAL_MIN    (0x80)      /**< 80ms */

#define CFG_FAST_CONN_ADV_INTERVAL_MAX    (0xA0)      /**< 100ms */
@@ -228,12 +240,13 @@ 
 * LsSource

 * Some information for Low speed clock mapped in bits field

 * - bit 0:   1: Calibration for the RF system wakeup clock source   0: No calibration for the RF system wakeup clock source

 * - bit 1:   1: STM32W5M Module device                              0: Other devices as STM32WBxx SOC, STM32WB1M module

 * - bit 1:   1: STM32WB5M Module device                             0: Other devices as STM32WBxx SOC, STM32WB1M module

 * - bit 2:   1: HSE/1024 Clock config                               0: LSE Clock config

 */

#if defined(STM32WB5Mxx)

  #define CFG_BLE_LSE_SOURCE  (SHCI_C2_BLE_INIT_CFG_BLE_LSE_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LSE_MOD5MM_DEV)

  #define CFG_BLE_LS_SOURCE  (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE)

#else

  #define CFG_BLE_LSE_SOURCE  (SHCI_C2_BLE_INIT_CFG_BLE_LSE_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LSE_OTHER_DEV)

  #define CFG_BLE_LS_SOURCE  (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE)

#endif



/**
@@ -265,6 +278,10 @@ 
 * - SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV

 * - SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2

 * - SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2

 * - SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM

 * - SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM

 * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED

 * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED

 * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1

 * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3

 * which are used to set following configuration bits:
@@ -278,12 +295,31 @@ 
 *          0: extended advertizing not supported

 * (bit 4): 1: CS Algo #2 supported

 *          0: CS Algo #2 not supported

 * (bit 5): 1: Reduced GATT database in NVM

 *          0: Full GATT database in NVM

 * (bit 6): 1: GATT caching is used

 *          0: GATT caching is not used

 * (bit 7): 1: LE Power Class 1

 *          0: LE Power Class 2-3

 * other bits: reserved (shall be set to 0)

 * other bits: complete with Options_extension flag

 */

/* Z-WB-3 */

#define CFG_BLE_OPTIONS  (SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY | SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC | SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW | SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV | SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 | SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3)

#define CFG_BLE_OPTIONS  (SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY | SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC | SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW | SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV | SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 | SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM | SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED | SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3)



/**

 * BLE stack Options_extension flags to be configured with:

 * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE

 * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY

 * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED

 * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED

 * which are used to set following configuration bits:

 * (bit 0): 1: appearance Writable

 *          0: appearance Read-Only

 * (bit 1): 1: Enhanced ATT supported

 *          0: Enhanced ATT not supported

 * other bits: reserved (shall be set to 0)

 */

#define CFG_BLE_OPTIONS_EXT  (SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY | SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED)



#define CFG_BLE_MAX_COC_INITIATOR_NBR   (32)
@@ -333,6 +369,15 @@ 


#define CFG_BLE_RX_PATH_COMPENS    (0)



  /* BLE core version (16-bit signed integer).

   * - SHCI_C2_BLE_INIT_BLE_CORE_5_2

   * - SHCI_C2_BLE_INIT_BLE_CORE_5_3

   * which are used to set: 11(5.2), 12(5.3).

   */



#define CFG_BLE_CORE_VERSION   (SHCI_C2_BLE_INIT_BLE_CORE_5_3)





/******************************************************************************

 * Transport Layer

 ******************************************************************************/

lib/stm32wb/hci/ble_bufsize.h

+17 −17
Changes for lib/stm32wb/hci/ble_bufsize.h: 17 added lines, 17 removed lines.
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 
 *****************************************************************************

 * @attention

 *

 * Copyright (c) 2018-2022 STMicroelectronics.

 * Copyright (c) 2018-2023 STMicroelectronics.

 * All rights reserved.

 *

 * This software is licensed under terms that can be found in the LICENSE file
@@ -77,47 +77,47 @@ 


/*

 * BLE_FIXED_BUFFER_SIZE_BYTES:

 * A part of the RAM, is dinamically allocated by initilizing all the pointers

 * A part of the RAM, is dynamically allocated by initializing all the pointers

 * defined in a global context variable "mem_alloc_ctx_p".

 * This initialization is made in the Dynamic_allocator functions, which

 * assing a portion of RAM given by the external application to the above

 * assign a portion of RAM given by the external application to the above

 * mentioned "global pointers".

 *

 * The size of this Dynamic RAM is made of 2 main components:

 * - a part that is parameters-dependent (num of links, GATT buffers, ...),

 *   and which value is explicited by the following macro;

 *   and which value is made explicit by the following macro;

 * - a part, that may be considered "fixed", i.e. independent from the above

 *   mentioned parameters.

*/

#if (BEACON_ONLY != 0)

#define BLE_FIXED_BUFFER_SIZE_BYTES  4076   /* Beacon only */

#define BLE_FIXED_BUFFER_SIZE_BYTES  4092   /* Beacon only */

#elif (LL_ONLY_BASIC != 0)

#define BLE_FIXED_BUFFER_SIZE_BYTES  5692   /* LL only Basic*/

#define BLE_FIXED_BUFFER_SIZE_BYTES  5788   /* LL only Basic*/

#elif (LL_ONLY != 0)

#define BLE_FIXED_BUFFER_SIZE_BYTES  5940   /* LL only Full */

#define BLE_FIXED_BUFFER_SIZE_BYTES  6036   /* LL only Full */

#elif (SLAVE_ONLY != 0)

#define BLE_FIXED_BUFFER_SIZE_BYTES  6204   /* Peripheral only */

#define BLE_FIXED_BUFFER_SIZE_BYTES  6292   /* Peripheral only */

#elif (BASIC_FEATURES != 0)

#define BLE_FIXED_BUFFER_SIZE_BYTES  6532   /* Basic Features */

#define BLE_FIXED_BUFFER_SIZE_BYTES  6624   /* Basic Features */

#else

#define BLE_FIXED_BUFFER_SIZE_BYTES  7056   /* Full stack */

#define BLE_FIXED_BUFFER_SIZE_BYTES  7144   /* Full stack */

#endif



/*

 * BLE_PER_LINK_SIZE_BYTES: additional memory size used per link

 */

#if (BEACON_ONLY != 0)

#define BLE_PER_LINK_SIZE_BYTES       128   /* Beacon only */

#define BLE_PER_LINK_SIZE_BYTES       112   /* Beacon only */

#elif (LL_ONLY_BASIC != 0)

#define BLE_PER_LINK_SIZE_BYTES       260   /* LL only Basic */

#define BLE_PER_LINK_SIZE_BYTES       244   /* LL only Basic */

#elif (LL_ONLY != 0)

#define BLE_PER_LINK_SIZE_BYTES       260   /* LL only Full */

#define BLE_PER_LINK_SIZE_BYTES       244   /* LL only Full */

#elif (SLAVE_ONLY != 0)

#define BLE_PER_LINK_SIZE_BYTES       392   /* Peripheral only */

#define BLE_PER_LINK_SIZE_BYTES       344   /* Peripheral only */

#elif (BASIC_FEATURES != 0)

#define BLE_PER_LINK_SIZE_BYTES       440   /* Basic Features */

#define BLE_PER_LINK_SIZE_BYTES       420   /* Basic Features */

#else

#define BLE_PER_LINK_SIZE_BYTES       444   /* Full stack */

#define BLE_PER_LINK_SIZE_BYTES       432   /* Full stack */

#endif



/*
@@ -148,7 +148,7 @@ 
 * Valid values are from 31 to 1650.

 */

#define BLE_EXT_ADV_BUFFER_SIZE(set_nbr, data_len) \

          (2304 + ((892 + (DIVC(data_len, 207) * 244)) * (set_nbr)))

          (2512 + ((892 + (DIVC(data_len, 207) * 244)) * (set_nbr)))



/*

 * BLE_TOTAL_BUFFER_SIZE_GATT: this macro returns the amount of memory,

lib/stm32wb/hci/shci.h

+53 −5
Changes for lib/stm32wb/hci/shci.h: 53 added lines, 5 removed lines.
Original line number Diff line number Diff line
@@ -495,6 +495,7 @@ extern "C" { 
   * Some information for Low speed clock mapped in bits field

   * - bit 0:   1: Calibration for the RF system wakeup clock source   0: No calibration for the RF system wakeup clock source

   * - bit 1:   1: STM32W5M Module device                              0: Other devices as STM32WBxx SOC, STM32WB1M module

   * - bit 2:   1: HSE/1024 Clock config                               0: LSE Clock config

   */

  uint8_t LsSource;
@@ -532,8 +533,10 @@ extern "C" { 
   * - bit 2:   1: device name Read-Only            0: device name R/W

   * - bit 3:   1: extended advertizing supported   0: extended advertizing not supported

   * - bit 4:   1: CS Algo #2 supported             0: CS Algo #2 not supported

   * - bit 5:   1: Reduced GATT database in NVM     0: Full GATT database in NVM

   * - bit 6:   1: GATT caching is used             0: GATT caching is not used

   * - bit 7:   1: LE Power Class 1                 0: LE Power Classe 2-3

   * - other bits: reserved ( shall be set to 0)

   * - other bits: complete with Options_extension flag

   */

  uint8_t Options;
@@ -594,6 +597,19 @@ extern "C" { 
   */

  int16_t rx_path_compens;



  /* BLE core specification version (8-bit unsigned integer).

   * values as: 11(5.2), 12(5.3)

   */

  uint8_t ble_core_version;



   /**

   * Options flags extension

   * - bit 0:   1: appearance Writable              0: appearance Read-Only

   * - bit 1:   1: Enhanced ATT supported           0: Enhanced ATT not supported

   * - other bits: reserved ( shall be set to 0)

   */

  uint8_t Options_extension;



      } SHCI_C2_Ble_Init_Cmd_Param_t;



  typedef PACKED_STRUCT{
@@ -621,22 +637,47 @@ extern "C" { 
#define SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2                             (1<<4)

#define SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2                          (0<<4)



#define SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM                     (1<<5)

#define SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM                      (0<<5)



#define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED                    (1<<6)

#define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED                 (0<<6)



#define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1                        (1<<7)

#define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3                      (0<<7)



  /**

   * Options extension

   * Each definition below may be added together to build the Options value

   * WARNING : Only one definition per bit shall be added to build the Options value

   */

#define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE                  (1<<0)

#define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY                  (0<<0)



#define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED               (1<<1)

#define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED            (0<<1)



    /**

   * RX models configuration

   */

#define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_LEGACY                     (0<<0)

#define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_BLOCKER                    (1<<0)



  /**

   * BLE core version

   */

#define SHCI_C2_BLE_INIT_BLE_CORE_5_2               11

#define SHCI_C2_BLE_INIT_BLE_CORE_5_3               12



   /**

   * LsSource information

   */

#define SHCI_C2_BLE_INIT_CFG_BLE_LSE_NOCALIB                     (0<<0)

#define SHCI_C2_BLE_INIT_CFG_BLE_LSE_CALIB                       (1<<0)

#define SHCI_C2_BLE_INIT_CFG_BLE_LSE_OTHER_DEV                   (0<<1)

#define SHCI_C2_BLE_INIT_CFG_BLE_LSE_MOD5MM_DEV                  (1<<1)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB                     (0<<0)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_CALIB                       (1<<0)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV                   (0<<1)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV                  (1<<1)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE                     (0<<2)

#define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_HSE_1024                (1<<2)



#define SHCI_OPCODE_C2_THREAD_INIT              (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)

/** No command parameters */
@@ -796,6 +837,7 @@ extern "C" { 
      uint32_t BleNvmRamAddress;

      uint32_t ThreadNvmRamAddress;

      uint16_t RevisionID;

      uint16_t DeviceID;

    } SHCI_C2_CONFIG_Cmd_Param_t;



#define SHCI_OPCODE_C2_802_15_4_DEINIT    (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT)
@@ -813,6 +855,12 @@ extern "C" { 
#define SHCI_C2_CONFIG_CUT2_1                        (0x2001)

#define SHCI_C2_CONFIG_CUT2_2                        (0x2003)



/**

 * Device ID

 */

#define SHCI_C2_CONFIG_STM32WB55xx                   (0x495)

#define SHCI_C2_CONFIG_STM32WB15xx                   (0x494)



/**

 * Config1

 * Each definition below may be added together to build the Config1 value

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