Commit 0d73e189 authored by Guillaume Gautier's avatar Guillaume Gautier Committed by Erwan Gouriou
Browse files

stm32cube: update stm32wb to cube version V1.16.0 

Update Cube version for STM32WBxx series
on https://github.com/STMicroelectronics
from version v1.14.0
to version v1.16.0

Signed-off-by: default avatarGuillaume Gautier <guillaume.gautier-ext@st.com>
parent 6e2594a8

stm32cube/stm32wbxx/README

+2 −2
Changes for stm32cube/stm32wbxx/README: 2 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubewb.html



Status:

   version v1.14.0

   version v1.16.0



Purpose:

   ST Microelectronics official MCU package for STM32WB series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeWB



Commit:

   83aacadecbd5136ad3194f39e002ff50a5439ad9

   2234d9783a661bd25dd626810b6a8cc7e58f7df2



Maintained-by:

   External

stm32cube/stm32wbxx/drivers/include/Legacy/stm32_hal_legacy.h

+362 −47

File changed.

Preview size limit exceeded, changes collapsed.

stm32cube/stm32wbxx/drivers/include/stm32wbxx_hal.h

+52 −38
Changes for stm32cube/stm32wbxx/drivers/include/stm32wbxx_hal.h: 52 added lines, 38 removed lines.
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ typedef enum 
#define SYSCFG_BOOT_SRAM                LL_SYSCFG_REMAP_SRAM            /*!< SRAM1 mapped at 0x00000000               */

#if defined(LL_SYSCFG_REMAP_QUADSPI)

#define SYSCFG_BOOT_QUADSPI             LL_SYSCFG_REMAP_QUADSPI         /*!< QUADSPI memory mapped at 0x00000000      */

#endif

#endif /* LL_SYSCFG_REMAP_QUADSPI */

/**

  * @}

  */
@@ -223,7 +223,7 @@ typedef enum 
  */

#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)

#define HAL_SYSCFG_SECURE_ACCESS_AES1   LL_SYSCFG_SECURE_ACCESS_AES1    /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */

#endif

#endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */

#define HAL_SYSCFG_SECURE_ACCESS_AES2   LL_SYSCFG_SECURE_ACCESS_AES2    /*!< Enabling the security access of Advanced Encryption Standard 2          */

#define HAL_SYSCFG_SECURE_ACCESS_PKA    LL_SYSCFG_SECURE_ACCESS_PKA     /*!< Enabling the security access of Public Key Accelerator                  */

#define HAL_SYSCFG_SECURE_ACCESS_RNG    LL_SYSCFG_SECURE_ACCESS_RNG     /*!< Enabling the security access of Random Number Generator                 */
@@ -257,57 +257,57 @@ typedef enum 
#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

#define __HAL_DBGMCU_FREEZE_TIM2()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

#define __HAL_DBGMCU_UNFREEZE_TIM2()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_TIM2_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)

#define __HAL_DBGMCU_FREEZE_RTC()               LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

#define __HAL_DBGMCU_UNFREEZE_RTC()             LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_RTC_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

#define __HAL_DBGMCU_FREEZE_WWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

#define __HAL_DBGMCU_UNFREEZE_WWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_WWDG_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

#define __HAL_DBGMCU_FREEZE_IWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

#define __HAL_DBGMCU_UNFREEZE_IWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_IWDG_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_I2C1_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_I2C3_STOP */



#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#define __HAL_DBGMCU_FREEZE_LPTIM1()            LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#define __HAL_DBGMCU_UNFREEZE_LPTIM1()          LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP1_LPTIM1_STOP */



#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#define __HAL_DBGMCU_FREEZE_LPTIM2()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#define __HAL_DBGMCU_UNFREEZE_LPTIM2()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#endif

#endif /* LL_DBGMCU_APB1_GRP2_LPTIM2_STOP */



#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

#define __HAL_DBGMCU_FREEZE_TIM1()              LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

#define __HAL_DBGMCU_UNFREEZE_TIM1()            LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)

#endif

#endif /* LL_DBGMCU_APB2_GRP1_TIM1_STOP */



#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

#define __HAL_DBGMCU_FREEZE_TIM16()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

#define __HAL_DBGMCU_UNFREEZE_TIM16()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)

#endif

#endif /* LL_DBGMCU_APB2_GRP1_TIM16_STOP */



#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

#define __HAL_DBGMCU_FREEZE_TIM17()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

#define __HAL_DBGMCU_UNFREEZE_TIM17()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)

#endif

#endif /* LL_DBGMCU_APB2_GRP1_TIM17_STOP */



/**

  * @}
@@ -319,52 +319,52 @@ typedef enum 
#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

#define __HAL_C2_DBGMCU_FREEZE_TIM2()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_TIM2()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

#define __HAL_C2_DBGMCU_FREEZE_RTC()            LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_RTC()          LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_RTC_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

#define __HAL_C2_DBGMCU_FREEZE_IWDG()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_IWDG()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#define __HAL_C2_DBGMCU_FREEZE_LPTIM1()         LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1()       LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP */



#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#define __HAL_C2_DBGMCU_FREEZE_LPTIM2()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP */



#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

#define __HAL_C2_DBGMCU_FREEZE_TIM1()           LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_TIM1()         LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP */



#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

#define __HAL_C2_DBGMCU_FREEZE_TIM16()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_TIM16()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP */



#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

#define __HAL_C2_DBGMCU_FREEZE_TIM17()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

#define __HAL_C2_DBGMCU_UNFREEZE_TIM17()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)

#endif

#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP */



/**

  * @}
@@ -394,7 +394,7 @@ typedef enum 
/** @brief  QUADSPI mapped at 0x00000000.

  */

#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()      LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)

#endif

#endif /* LL_SYSCFG_REMAP_QUADSPI */



/**

  * @brief  Return the boot mode as configured by user.
@@ -415,7 +415,9 @@ typedef enum 
  */

/* Legacy define */

#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE      __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\

#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)   \

  do {                                                     \

    assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__))); \

    LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);       \

  } while(0)
@@ -423,7 +425,9 @@ typedef enum 
  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63

  * @note   Write protection can only be disabled by a system reset

  */

#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__)));\

#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__)   \

  do {                                                      \

    assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__))); \

    LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);       \

  } while(0)
@@ -440,11 +444,15 @@ typedef enum 
/** @brief  Floating Point Unit interrupt enable/disable macros

  * @param __INTERRUPT__  This parameter can be a value of @ref SYSCFG_FPU_Interrupts

  */

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    \

  do {                                                      \

    assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \

    SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));                \

  } while(0)



#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   \

  do {                                                      \

    assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \

    CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));              \

  } while(0)
@@ -461,7 +469,8 @@ typedef enum 
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)



/** @brief  SYSCFG Break PVD lock.

  *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

  *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0]

  *         in the PWR_CR2 register.

  * @note   The selected configuration is locked and can be unlocked only by system reset.

  */

#define __HAL_SYSCFG_BREAK_PVD_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
@@ -479,7 +488,8 @@ typedef enum 
  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing

  * @retval The new state of __FLAG__ (TRUE or FALSE).

  */

#define __HAL_SYSCFG_GET_FLAG(__FLAG__)         ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)

#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & \

                                                (__FLAG__))!= 0U) ? 1U : 0U)



/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.

  */
@@ -488,11 +498,15 @@ typedef enum 
/** @brief  Fast mode Plus driving capability enable/disable macros

  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO

  */

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)    \

  do {                                                        \

    assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

    LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \

  } while(0)



#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__)   \

  do {                                                        \

    assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \

    LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \

  } while(0)
@@ -520,13 +534,13 @@ typedef enum 
                                                       (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \

                                                       (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))



#if defined(STM32WB15xx)

#if defined(STM32WB15xx) || defined(STM32WB10xx)

#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))

#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__)              (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU))

#else

#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))

#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__)              IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)

#endif

#endif /* STM32WB15xx || STM32WB10xx */



#if defined(VREFBUF)

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)      (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
@@ -536,7 +550,7 @@ typedef enum 
                                                         ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))



#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

#endif

#endif /* VREFBUF */



#define IS_SYSCFG_FASTMODEPLUS(__PIN__)                 ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6)  || \

                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)  || \
@@ -552,7 +566,7 @@ typedef enum 
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__)            ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \

                                                         (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA)  == HAL_SYSCFG_SECURE_ACCESS_PKA)  || \

                                                         (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG)  == HAL_SYSCFG_SECURE_ACCESS_RNG))

#endif

#endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */



/**

  * @}
@@ -660,14 +674,14 @@ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);

void HAL_SYSCFG_DisableVREFBUF(void);

#endif

#endif /* VREFBUF */



void HAL_SYSCFG_EnableIOBooster(void);

void HAL_SYSCFG_DisableIOBooster(void);

#if defined(SYSCFG_CFGR1_ANASWVDD)

void HAL_SYSCFG_EnableIOVdd(void);

void HAL_SYSCFG_DisableIOVdd(void);

#endif

#endif /* SYSCFG_CFGR1_ANASWVDD */



void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);

void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);

stm32cube/stm32wbxx/drivers/include/stm32wbxx_hal_adc.h

+28 −28
Changes for stm32cube/stm32wbxx/drivers/include/stm32wbxx_hal_adc.h: 28 added lines, 28 removed lines.
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ typedef struct 
                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */



} ADC_OversamplingTypeDef;

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/**

  * @brief  Structure definition of ADC instance and ADC group regular.
@@ -140,7 +140,7 @@ typedef struct 
                                       This parameter can be set to ENABLE or DISABLE.

                                       Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */



#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,

                                       after the first ADC conversion start trigger occurred (software start or external trigger).

                                       This parameter can be set to ENABLE or DISABLE. */
@@ -163,7 +163,7 @@ typedef struct 
  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.

                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.

                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.

                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
@@ -208,7 +208,7 @@ typedef struct 
                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),

                                             sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)

                                             Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



#if !defined(ADC_SUPPORT_2_5_MSPS)

  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
@@ -217,7 +217,7 @@ typedef struct 


  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.

                                               Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */

#endif

#endif /* !ADC_SUPPORT_2_5_MSPS */



#if defined(ADC_SUPPORT_2_5_MSPS)

  uint32_t TriggerFrequencyMode;  /*!< Set ADC trigger frequency mode.
@@ -230,7 +230,7 @@ typedef struct 
                                       Note: When ADC trigger frequency mode is set to low frequency,

                                             some rearm cycles are inserted before performing ADC conversion

                                             start, inducing a delay of 2 ADC clock cycles. */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



} ADC_InitTypeDef;
@@ -291,7 +291,7 @@ typedef struct 
                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled

                                              without continuous mode or external trigger that could launch a conversion). */



#endif

#endif /* !ADC_SUPPORT_2_5_MSPS */

} ADC_ChannelConfTypeDef;



/**
@@ -422,7 +422,7 @@ typedef struct 
  uint32_t                      ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */

#else

  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */

  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
@@ -589,7 +589,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

#define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

/**

  * @}

  */
@@ -655,7 +655,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */

#define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */

#define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

/**

  * @}

  */
@@ -699,7 +699,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
/**

  * @}

  */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number

  * @{
@@ -741,7 +741,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#else

#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */

#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

/**

  * @}

  */
@@ -793,7 +793,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
/**

  * @}

  */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

  * @{
@@ -822,7 +822,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
/**

  * @}

  */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */





/** @defgroup ADC_Event_type ADC Event type
@@ -835,7 +835,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */

#if !defined(ADC_SUPPORT_2_5_MSPS)

#define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */

#endif

#endif /* !ADC_SUPPORT_2_5_MSPS */

/**

  * @}

  */
@@ -856,7 +856,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */

#define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */

#define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */

#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */

#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
@@ -882,7 +882,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */

#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */

#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */

#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */

#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */

#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
@@ -944,7 +944,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL)))

#else

#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */





/**
@@ -1044,7 +1044,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \

                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)  || \

                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/**

  * @brief Verify the ADC regular conversions check for converted data availability.
@@ -1065,7 +1065,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
#if defined(ADC_SUPPORT_2_5_MSPS)

#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \

                                                           ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2)   )

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/**

  * @brief Verify the ADC conversions sampling time.
@@ -1090,12 +1090,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \

                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \

                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



#if defined(ADC_SUPPORT_2_5_MSPS)

#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \

                                             ((RANK) == ADC_RANK_NONE)             )

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/**

  * @brief Verify the ADC regular channel setting.
@@ -1157,7 +1157,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 


#if defined(ADC_SUPPORT_2_5_MSPS)

#define ADC_SCAN_SEQ_FIXED_INT  0x80000000U  /* Internal definition to differentiate sequencer setting fixed or configurable */

#endif

#endif /* ADC_SUPPORT_2_5_MSPS */



/**

  * @}
@@ -1823,7 +1823,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa 
HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);



/* ADC retrieve conversion value intended to be used with polling or interruption */

uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);

uint32_t                HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);



/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */

void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
@@ -1840,8 +1840,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 
  * @{

  */

/* Peripheral Control functions ***********************************************/

HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);

HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);

HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig);

HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);



/**

  * @}
@@ -1851,8 +1851,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana 
/** @addtogroup ADC_Exported_Functions_Group4

  * @{

  */

uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);

uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);

uint32_t                HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);

uint32_t                HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);



/**

  * @}

stm32cube/stm32wbxx/drivers/include/stm32wbxx_hal_adc_ex.h

+14 −14

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