Commit 6773ea7c authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Kumar Gala
Browse files

stm32cube: update stm32f0 to version V1.11.2 

Update Cube version for STM32F0xx series
on https://github.com/STMicroelectronics


from version v1.11.1
to version v1.11.2

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent 32e61c2a

stm32cube/stm32f0xx/README

+2 −10
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubef0.html



Status:

   version v1.11.1

   version v1.11.2



Purpose:

   ST Microelectronics official MCU package for STM32F0 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeF0



Commit:

   7b44872c87d4ef209386bb6bebe821f4b526b576

   4390ff6bfb693104cf97192f98c3dc9e3a7c296a



Maintained-by:

   External
@@ -40,12 +40,4 @@ Patch List: 
    -dos2unix applied

    -trailing white spaces removed



    *Extend public SetFlashLatency API to all families

     The LL_SetFlashLatency public API is now defined for families

     beyond G4, L4 and L5. The private function has been made public.

    Impacted files:

     drivers/include/stm32f0xx_ll_utils.h

     drivers/src/stm32f0xx_ll_utils.c

    ST Bug tracker ID: 76117



   See release_note.html from STM32Cube

stm32cube/stm32f0xx/drivers/include/Legacy/stm32_hal_legacy.h

+162 −26
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR



/**

  * @}

  */
@@ -236,12 +235,12 @@ 
#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE

#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE



#if defined(STM32G4)

#define DAC_CHIPCONNECT_DISABLE       (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)

#define DAC_CHIPCONNECT_ENABLE        (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)

#if defined(STM32G4) || defined(STM32H7)

#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL

#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL

#endif



#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)

#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)

#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID

#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID

#endif
@@ -306,8 +305,22 @@ 
#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING

#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING



#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)

#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI

#endif



#endif /* STM32L4 */



#if defined(STM32G0)

#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1

#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2

#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM

#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM



#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM

#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM

#endif



#if defined(STM32H7)



#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -365,6 +378,9 @@ 
#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT

#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT



#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT

#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT



#endif /* STM32H7 */



/**
@@ -566,7 +582,14 @@ 
#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2

#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2

#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2

#endif



#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \

    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)

#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS

#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS

#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS

#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */

#endif /* STM32H7 */



#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1

#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
@@ -624,6 +647,10 @@ 
#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable

#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable

#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset

#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A

#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B

#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL

#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL

#endif /* STM32G4 */



#if defined(STM32H7)
@@ -737,6 +764,66 @@ 
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

#endif /* STM32H7 */



#if defined(STM32F3)

/** @brief Constants defining available sources associated to external events.

  */

#define HRTIM_EVENTSRC_1              (0x00000000U)

#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)

#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)



/** @brief Constants defining the events that can be selected to configure the

  *        set/reset crossbar of a timer output

  */

#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)



#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)



/** @brief Constants defining the event filtering applied to external events

  *        by a timer

  */

#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)



/** @brief Constants defining the DLL calibration periods (in micro seconds)

  */

#define HRTIM_CALIBRATIONRATE_7300             0x00000000U

#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)

#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)

#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)



#endif /* STM32F3 */

/**

  * @}

  */
@@ -876,7 +963,7 @@ 
#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0

#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1



#if defined(STM32L1) || defined(STM32L4)

#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)

#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID

#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

#endif
@@ -967,6 +1054,16 @@ 
#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1

#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1



#if defined(STM32H7)

#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X

#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT



#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1

#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2

#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3

#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL

#endif /* STM32H7 */



/**

  * @}

  */
@@ -1360,6 +1457,30 @@ 


#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY



#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)



#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End

#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT

#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT



#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt

#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End

#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT

#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT



#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt

#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End

#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT

#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT



#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt

#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End

#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT



#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */

/**

  * @}

  */
@@ -1382,6 +1503,13 @@ 
#endif

#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode

#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode

#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode

#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */



/**

  * @}

  */
@@ -1411,16 +1539,18 @@ 


#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))



#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)

#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)

#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT

#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT

#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT

#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT

#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */

#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)

#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA

#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA

#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA

#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA

#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */

#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */



#if defined(STM32F4)

#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1439,6 +1569,13 @@ 
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose

  * @{

  */



#if defined(STM32G0)

#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD

#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD

#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD

#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler

#endif

#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD

#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg

#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
@@ -1511,14 +1648,14 @@ 
#define HAL_TIM_DMAError                                TIM_DMAError

#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt

#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt

#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)

#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)

#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro

#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT

#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback

#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent

#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT

#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA

#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */

#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */

/**

  * @}

  */
@@ -3114,9 +3251,8 @@ 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2



#if defined(STM32L4)

#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)

#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)

#else

#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK

#endif
@@ -3244,7 +3380,7 @@ 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

#else

#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

#endif
@@ -3367,7 +3503,7 @@ 
#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef

#endif



#if defined(STM32H7)

#if defined(STM32H7) || defined(STM32L5)

#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback

#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback

#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3622,9 +3758,9 @@ 
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined (STM32L4)

#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)

#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE

#endif

#endif /* STM32L4 || STM32F4 || STM32F7 */

/**

  * @}

  */

stm32cube/stm32f0xx/drivers/include/stm32f0xx_hal_cec.h

+2 −2
Original line number Diff line number Diff line
@@ -121,7 +121,7 @@ typedef struct 
  *          b6  Error information

  *             0  : No Error

  *             1  : Error

  *          b5     IP initilisation status

  *          b5     IP initialization status

  *             0  : Reset (IP not initialized)

  *             1  : Init done (IP initialized. HAL CEC Init function already called)

  *          b4-b3  (not used)
@@ -138,7 +138,7 @@ typedef struct 
  *          RxState value coding follow below described bitmap :

  *          b7-b6  (not used)

  *             xx : Should be set to 00

  *          b5     IP initilisation status

  *          b5     IP initialization status

  *             0  : Reset (IP not initialized)

  *             1  : Init done (IP initialized)

  *          b4-b2  (not used)

stm32cube/stm32f0xx/drivers/include/stm32f0xx_hal_def.h

+21 −9
Original line number Diff line number Diff line
@@ -28,9 +28,7 @@ 


/* Includes ------------------------------------------------------------------*/

#include "stm32f0xx.h"

#if defined(USE_HAL_LEGACY)

#include "Legacy/stm32_hal_legacy.h"

#endif /* USE_HAL_LEGACY */

#include <stddef.h>



/* Exported types ------------------------------------------------------------*/
@@ -109,7 +107,14 @@ typedef enum 
                                    }while (0U)

#endif /* USE_RTOS */



#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */

  #ifndef __weak

    #define __weak  __attribute__((weak))

  #endif

  #ifndef __packed

    #define __packed  __attribute__((packed))

  #endif

#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

  #ifndef __weak

    #define __weak   __attribute__((weak))

  #endif /* __weak */
@@ -120,7 +125,14 @@ typedef enum 




/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */

#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */

  #ifndef __ALIGN_BEGIN

    #define __ALIGN_BEGIN

  #endif

  #ifndef __ALIGN_END

    #define __ALIGN_END      __attribute__ ((aligned (4)))

  #endif

#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */

  #ifndef __ALIGN_END

    #define __ALIGN_END    __attribute__ ((aligned (4)))

  #endif /* __ALIGN_END */
@@ -132,7 +144,7 @@ typedef enum 
    #define __ALIGN_END

  #endif /* __ALIGN_END */

  #ifndef __ALIGN_BEGIN

    #if defined   (__CC_ARM)      /* ARM Compiler */

    #if defined   (__CC_ARM)      /* ARM Compiler V5*/

      #define __ALIGN_BEGIN    __align(4)

    #elif defined (__ICCARM__)    /* IAR Compiler */

      #define __ALIGN_BEGIN
@@ -143,9 +155,9 @@ typedef enum 
/**

  * @brief  __NOINLINE definition

  */

#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )

/* ARM & GNUCompiler

   ----------------

#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )

/* ARM V4/V5 and V6 & GNU Compiler

   -------------------------------

*/

#define __NOINLINE __attribute__ ( (noinline) )

stm32cube/stm32f0xx/drivers/include/stm32f0xx_hal_exti.h

+10 −10
Original line number Diff line number Diff line
@@ -278,20 +278,20 @@ typedef struct 
/** @defgroup EXTI_Private_Macros EXTI Private Macros

  * @{

  */

#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \

                                        ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \

                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \

                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \

                                         (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))

#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \

                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \

                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \

                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \

                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))



#define IS_EXTI_MODE(__LINE__)          ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \

                                         (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))

#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \

                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))



#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)

#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)



#define IS_EXTI_PENDING_EDGE(__LINE__)  ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)

#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)



#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00u)

#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)



#if defined (GPIOE)

#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \

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