Commit 41d443d3 authored by F. Ramu's avatar F. Ramu Committed by Erwan Gouriou
Browse files

stm32cube: update stm32u5 to cube version V1.8.0 

Update Cube version for STM32U5xx series
on https://github.com/STMicroelectronics


from version v1.7.0
to version v1.8.0

Signed-off-by: default avatarF. Ramu <francois.ramu@st.com>
parent cb7f6cbf

stm32cube/stm32u5xx/README

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubeu5.html



Status:

   version v1.7.0

   version v1.8.0



Purpose:

   ST Microelectronics official MCU package for STM32U5 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeU5



Commit:

   7392378474639cdcd87a71918f5272f847454055

   07b6fedf4b0670eb45d8806176bcc77167f42124



Maintained-by:

   External

stm32cube/stm32u5xx/drivers/include/Legacy/stm32_hal_legacy.h

+16 −8
Original line number Diff line number Diff line
@@ -538,6 +538,10 @@ extern "C" { 
#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE

#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL

#endif /* STM32H7 */

#if defined(STM32H7RS)

#define FLASH_OPTKEY1                 FLASH_OPT_KEY1

#define FLASH_OPTKEY2                 FLASH_OPT_KEY2

#endif /* STM32H7RS */

#if defined(STM32U5)

#define OB_USER_nRST_STOP             OB_USER_NRST_STOP

#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
@@ -560,6 +564,9 @@ extern "C" { 
#define OB_nBOOT0_RESET               OB_NBOOT0_RESET

#define OB_nBOOT0_SET                 OB_NBOOT0_SET

#endif /* STM32U0 */

#if defined(STM32H5)

#define FLASH_ECC_AREA_EDATA          FLASH_ECC_AREA_EDATA_BANK1

#endif /* STM32H5 */



/**

  * @}
@@ -1299,22 +1306,22 @@ extern "C" { 
#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL

#endif /* STM32H5 || STM32WBA || STM32H7RS ||  STM32N6 */



#if defined(STM32F7)

#if defined(STM32F7) || defined(STM32WB)

#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK

#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK

#endif /* STM32F7 */

#endif /* STM32F7 || STM32WB */



#if defined(STM32H7)

#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X

#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT

#endif /* STM32H7 */



#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)

#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)

#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1

#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2

#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3

#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP

#endif /* STM32F7 || STM32H7 || STM32L0 */

#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */



/**

  * @}
@@ -1481,7 +1488,7 @@ extern "C" { 
#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2

#endif



#if defined(STM32U5)

#if defined(STM32U5) || defined(STM32MP2)

#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS

#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK

#endif
@@ -3695,7 +3702,8 @@ extern "C" { 
#endif



#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \

    defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)

      defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \

      defined(STM32U0)

#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

#else

#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3946,8 +3954,8 @@ extern "C" { 
  */

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \

    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \

    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \

    defined (STM32H7RS) ||  defined (STM32U0) || defined (STM32U3)

    defined (STM32WBA) || defined (STM32H5) || \

    defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) ||  defined (STM32U0) || defined (STM32U3)

#else

#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

#endif

stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_dma_ex.h

+26 −26
Original line number Diff line number Diff line
@@ -596,40 +596,40 @@ typedef struct 
  * @brief    DMAEx Private Constants

  * @{

  */

#define DMA_LINKEDLIST                  (0x0080U) /* DMA channel linked-list mode          */

#define DMA_LINKEDLIST                  (0x0080UL) /* DMA channel linked-list mode          */



#define DMA_CHANNEL_TYPE_LINEAR_ADDR    (0x0001U) /* DMA channel linear addressing mode    */

#define DMA_CHANNEL_TYPE_2D_ADDR        (0x0002U) /* DMA channel 2D addressing mode        */

#define DMA_CHANNEL_TYPE_LPDMA          (0x0010U) /* LPDMA channel node                    */

#define DMA_CHANNEL_TYPE_GPDMA          (0x0020U) /* GPDMA channel node                    */

#define DMA_CHANNEL_TYPE_LINEAR_ADDR    (0x0001UL) /* DMA channel linear addressing mode    */

#define DMA_CHANNEL_TYPE_2D_ADDR        (0x0002UL) /* DMA channel 2D addressing mode        */

#define DMA_CHANNEL_TYPE_LPDMA          (0x0010UL) /* LPDMA channel node                    */

#define DMA_CHANNEL_TYPE_GPDMA          (0x0020UL) /* GPDMA channel node                    */



#define NODE_TYPE_MASK                  (0x00FFU) /* DMA channel node type                 */

#define NODE_CLLR_IDX                   (0x0700U) /* DMA channel node CLLR index mask      */

#define NODE_CLLR_IDX_POS               (0x0008U) /* DMA channel node CLLR index position  */

#define NODE_TYPE_MASK                  (0x00FFUL) /* DMA channel node type                 */

#define NODE_CLLR_IDX                   (0x0700UL) /* DMA channel node CLLR index mask      */

#define NODE_CLLR_IDX_POS               (0x0008UL) /* DMA channel node CLLR index position  */



#define NODE_MAXIMUM_SIZE               (0x0008U) /* Amount of registers of the node       */

#define NODE_MAXIMUM_SIZE               (0x0008UL) /* Amount of registers of the node       */



#define NODE_STATIC_FORMAT              (0x0000U) /* DMA channel node static format        */

#define NODE_DYNAMIC_FORMAT             (0x0001U) /* DMA channel node dynamic format       */

#define NODE_STATIC_FORMAT              (0x0000UL) /* DMA channel node static format        */

#define NODE_DYNAMIC_FORMAT             (0x0001UL) /* DMA channel node dynamic format       */



#define UPDATE_CLLR_POSITION            (0x0000U) /* DMA channel update CLLR position      */

#define UPDATE_CLLR_VALUE               (0x0001U) /* DMA channel update CLLR value         */

#define UPDATE_CLLR_POSITION            (0x0000UL) /* DMA channel update CLLR position      */

#define UPDATE_CLLR_VALUE               (0x0001UL) /* DMA channel update CLLR value         */



#define LASTNODE_ISNOT_CIRCULAR         (0x0000U) /* Last node is not first circular node  */

#define LASTNODE_IS_CIRCULAR            (0x0001U) /* Last node is first circular node      */

#define LASTNODE_ISNOT_CIRCULAR         (0x0000UL) /* Last node is not first circular node  */

#define LASTNODE_IS_CIRCULAR            (0x0001UL) /* Last node is first circular node      */



#define QUEUE_TYPE_STATIC               (0x0000U) /* DMA channel static queue              */

#define QUEUE_TYPE_DYNAMIC              (0x0001U) /* DMA channel dynamic queue             */

#define QUEUE_TYPE_STATIC               (0x0000UL) /* DMA channel static queue              */

#define QUEUE_TYPE_DYNAMIC              (0x0001UL) /* DMA channel dynamic queue             */



#define NODE_CTR1_DEFAULT_OFFSET        (0x0000U) /* CTR1 default offset                   */

#define NODE_CTR2_DEFAULT_OFFSET        (0x0001U) /* CTR2 default offset                   */

#define NODE_CBR1_DEFAULT_OFFSET        (0x0002U) /* CBR1 default offset                   */

#define NODE_CSAR_DEFAULT_OFFSET        (0x0003U) /* CSAR default offset                   */

#define NODE_CDAR_DEFAULT_OFFSET        (0x0004U) /* CDAR default offset                   */

#define NODE_CTR3_DEFAULT_OFFSET        (0x0005U) /* CTR3 2D addressing default offset     */

#define NODE_CBR2_DEFAULT_OFFSET        (0x0006U) /* CBR2 2D addressing default offset     */

#define NODE_CLLR_2D_DEFAULT_OFFSET     (0x0007U) /* CLLR 2D addressing default offset     */

#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */

#define NODE_CTR1_DEFAULT_OFFSET        (0x0000UL) /* CTR1 default offset                   */

#define NODE_CTR2_DEFAULT_OFFSET        (0x0001UL) /* CTR2 default offset                   */

#define NODE_CBR1_DEFAULT_OFFSET        (0x0002UL) /* CBR1 default offset                   */

#define NODE_CSAR_DEFAULT_OFFSET        (0x0003UL) /* CSAR default offset                   */

#define NODE_CDAR_DEFAULT_OFFSET        (0x0004UL) /* CDAR default offset                   */

#define NODE_CTR3_DEFAULT_OFFSET        (0x0005UL) /* CTR3 2D addressing default offset     */

#define NODE_CBR2_DEFAULT_OFFSET        (0x0006UL) /* CBR2 2D addressing default offset     */

#define NODE_CLLR_2D_DEFAULT_OFFSET     (0x0007UL) /* CLLR 2D addressing default offset     */

#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */



#define DMA_BURST_ADDR_OFFSET_MIN       (-8192L)  /* DMA burst minimum address offset      */

#define DMA_BURST_ADDR_OFFSET_MAX       (8192L)   /* DMA burst maximum address offset      */

stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_exti.h

+8 −8
Original line number Diff line number Diff line
@@ -201,19 +201,19 @@ typedef struct 
/**

  * @brief  EXTI Line property definition

  */

#define EXTI_PROPERTY_SHIFT                  24U

#define EXTI_DIRECT                         (0x01U << EXTI_PROPERTY_SHIFT)

#define EXTI_CONFIG                         (0x02U << EXTI_PROPERTY_SHIFT)

#define EXTI_GPIO                           ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

#define EXTI_RESERVED                       (0x08U << EXTI_PROPERTY_SHIFT)

#define EXTI_PROPERTY_SHIFT                  24UL

#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)

#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)

#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)

#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)



/**

  * @brief  EXTI Register and bit usage

  */

#define EXTI_REG_SHIFT                      16U

#define EXTI_REG1                           (0x00U << EXTI_REG_SHIFT)

#define EXTI_REG2                           (0x01U << EXTI_REG_SHIFT)

#define EXTI_REG_SHIFT                      16UL

#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)

#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)

#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)

#define EXTI_PIN_MASK                       0x0000001FU

stm32cube/stm32u5xx/drivers/include/stm32u5xx_hal_hcd.h

+4 −0
Original line number Diff line number Diff line
@@ -134,6 +134,9 @@ typedef struct 
/** @defgroup HCD_Exported_Constants HCD Exported Constants

  * @{

  */

#ifndef HAL_HCD_CHANNEL_NAK_COUNT

#define HAL_HCD_CHANNEL_NAK_COUNT           2U

#endif /* HAL_HCD_CHANNEL_NAK_COUNT */



/** @defgroup HCD_Speed HCD Speed

  * @{
@@ -232,6 +235,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, 
                                  uint8_t speed, uint8_t ep_type, uint16_t mps);



HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);

HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num);

#if defined (USB_DRD_FS)

HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);

#endif /* defined (USB_DRD_FS) */

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