Commit 0450703a authored by Francois Ramu's avatar Francois Ramu Committed by Kumar Gala
Browse files

stm32cube: update stm32h7 to version V1.9.0 

Update Cube version for STM32H7xx series
on https://github.com/STMicroelectronics


from version v1.8.0
to version v1.9.0

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 10c19f34

stm32cube/stm32h7xx/README

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Origin: 
   http://www.st.com/en/embedded-software/stm32cubeh7.html



Status:

   version v1.8.0

   version v1.9.0



Purpose:

   ST Microelectronics official MCU package for STM32H7 series.
@@ -23,7 +23,7 @@ URL: 
   https://github.com/STMicroelectronics/STM32CubeH7



Commit:

   beced99ac090fece04d1e0eb6648b8075e156c6c

   ccb11556044540590ca6e45056e6b65cdca2deb2



Maintained-by:

   External

stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h

+74 −101
Original line number Diff line number Diff line
@@ -38,7 +38,6 @@ 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR



/**

  * @}

  */
@@ -384,6 +383,7 @@ 


#endif /* STM32H7 */





/**

  * @}

  */
@@ -596,12 +596,12 @@ 
#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1



#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)

#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)

#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW

#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM

#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH

#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/



#if defined(STM32L1)

#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
@@ -774,49 +774,6 @@ 
#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)



/** @brief Constants defining the events that can be selected to configure the

  *        set/reset crossbar of a timer output

  */

#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)



#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)



/** @brief Constants defining the event filtering applied to external events

  *        by a timer

  */

#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)



/** @brief Constants defining the DLL calibration periods (in micro seconds)

  */

#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
@@ -969,6 +926,11 @@ 
#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

#endif



#if defined(STM32L4) || defined(STM32L5)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER

#elif defined(STM32G4)

#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED

#endif



/**

  * @}
@@ -1459,7 +1421,7 @@ 
#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY



#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)

#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)



#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
@@ -1481,7 +1443,7 @@ 
#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT



#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */

#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */

/**

  * @}

  */
@@ -1495,7 +1457,8 @@ 
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode

#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode

#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\

                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect

#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())

#if defined(STM32L0)
@@ -1503,7 +1466,8 @@ 
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())

#endif

#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\

                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
@@ -1538,7 +1502,8 @@ 
#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter

#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter



#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))

#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\

                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))



#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)

#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
@@ -2284,7 +2249,8 @@ 
#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI



#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\

                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())



#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE

#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
@@ -3252,7 +3218,7 @@ 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2



#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)

#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)

#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

#else

#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3381,7 +3347,7 @@ 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)

#else

#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

#endif
@@ -3597,6 +3563,13 @@ 
#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE

#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE



#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)

#define USART_OVERSAMPLING_16               0x00000000U

#define USART_OVERSAMPLING_8                USART_CR1_OVER8



#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \

                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

#endif /* STM32F0 || STM32F3 || STM32F7 */

/**

  * @}

  */

stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h

+8 −4
Original line number Diff line number Diff line
@@ -69,10 +69,10 @@ typedef enum 
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale

  * @{

  */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 0 (VREF_OUT1) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 1 (VREF_OUT2) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 2 (VREF_OUT3) */

#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 3 (VREF_OUT4) */





#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
@@ -1093,10 +1093,14 @@ void HAL_DisableDomain2DBGStopMode(void); 
void HAL_EnableDomain2DBGStandbyMode(void);

void HAL_DisableDomain2DBGStandbyMode(void);

#endif /*DUAL_CORE*/

#if defined(DBGMCU_CR_DBG_STOPD3)

void HAL_EnableDomain3DBGStopMode(void);

void HAL_DisableDomain3DBGStopMode(void);

#endif /*DBGMCU_CR_DBG_STOPD3*/

#if defined(DBGMCU_CR_DBG_STANDBYD3)

void HAL_EnableDomain3DBGStandbyMode(void);

void HAL_DisableDomain3DBGStandbyMode(void);

#endif /*DBGMCU_CR_DBG_STANDBYD3*/

void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );

void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);

#if defined(DUAL_CORE)

stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h

+11 −11
Original line number Diff line number Diff line
@@ -128,11 +128,11 @@ typedef struct 
                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun

                                       for low frequency applications.

                                       This parameter can be set to ENABLE or DISABLE.

                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag

                                             to free the IRQ vector sequencer.

                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).

                                                       Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).

                                                       Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:

                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.

                                             (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */

													   and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group,

													   use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */



  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,

                                       after the first ADC conversion start trigger occurred (software start or external trigger).
@@ -163,7 +163,7 @@ typedef struct 
                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.

                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */



  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.

  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register.

                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.

                                       This parameter can be a value of @ref ADC_ConversionDataManagement.

                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups
@@ -266,7 +266,7 @@ typedef struct 
                                        This parameter is applied only for 16-bit or 8-bit resolution.

                                        This parameter can be set to ENABLE or DISABLE.*/

#if defined(ADC_VER_V5_V90)

  uint32_t OffsetSign;                /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.

  uint32_t OffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.

                                        This parameter can be a value of @ref ADCEx_OffsetSign.

                                        Note:

                                              - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
@@ -380,7 +380,7 @@ typedef struct 
                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */

#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */

#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */

#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 serie: End Of Sampling flag raised  */

#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag raised  */



/* States of ADC group injected */

#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
@@ -533,7 +533,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
  * @{

  */

#define ADC3_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT)      /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/

#define ADC3_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/

#define ADC3_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/

/**

  * @}

  */
@@ -1773,7 +1773,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
  *         connected to pin Vref+.

  *         On devices with small package, the pin Vref+ is not present

  *         and internally bonded to pin Vdda.

  * @note   On this STM32 serie, calibration data of internal voltage reference

  * @note   On this STM32 series, calibration data of internal voltage reference

  *         VrefInt corresponds to a resolution of 12 bits,

  *         this is the recommended ADC resolution to convert voltage of

  *         internal voltage reference VrefInt.
@@ -1821,7 +1821,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to 
  * @note   Analog reference voltage (Vref+) must be either known from

  *         user board environment or can be calculated using ADC measurement

  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  * @note   On this STM32 serie, calibration data of temperature sensor

  * @note   On this STM32 series, calibration data of temperature sensor

  *         corresponds to a resolution of 12 bits,

  *         this is the recommended ADC resolution to convert voltage of

  *         temperature sensor.

stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h

+8 −5
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ typedef struct 
                                                This parameter is applied only for 16-bit or 8-bit resolution.

                                                This parameter can be set to ENABLE or DISABLE. */

#if defined(ADC_VER_V5_V90)

  uint32_t InjectedOffsetSign;                /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.

  uint32_t InjectedOffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.

                                               This parameter can be a value of @ref ADCEx_OffsetSign.

                                               Note:

                                                     - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
@@ -295,7 +295,7 @@ typedef struct 
/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign

  * @{

  */

#define ADC3_OFFSET_SIGN_NEGATIVE      (0x00000000UL)          /*!< Offset sign negative, offset is substracted */

#define ADC3_OFFSET_SIGN_NEGATIVE      (0x00000000UL)          /*!< Offset sign negative, offset is subtracted */

#define ADC3_OFFSET_SIGN_POSITIVE      (ADC3_OFR1_OFFSETPOS)   /*!< Offset sign positive, offset is added  */

/**

  * @}
@@ -415,7 +415,7 @@ typedef struct 
  * @{

  */

#define ADC_DFSDM_MODE_DISABLE     (0x00000000UL)                     /*!< ADC conversions are not transferred by DFSDM. */

#define ADC_DFSDM_MODE_ENABLE      (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */

#define ADC_DFSDM_MODE_ENABLE      (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */

/**

  * @}

  */
@@ -441,7 +441,7 @@ typedef struct 
  *         Usage of this macro is not the Standard way of multimode

  *         configuration and can lead to have HAL ADC handles status

  *         misaligned. Usage of this macro must be limited to cases

  *         mentionned above.

  *         mentioned above.

  * @param __HANDLE__ ADC handle.

  * @retval None

  */
@@ -1207,7 +1207,10 @@ typedef struct 
                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_9   ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_10  ) || \

                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_11  ))



/**

  * @brief Verify the ADC oversampling triggered mode.

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