Commit 9742ff58 authored by GuentherMartin's avatar GuentherMartin Committed by Jonatan Antoni
Browse files

Core: Added CoreDebug, CMSIS_5 backward compatibility

parent 6c0d0b2b

CMSIS/Core/Include/core_cm23.h

+94 −0
Original line number Diff line number Diff line
@@ -1285,6 +1285,100 @@ typedef struct 
#define SCB_AIRCR_ENDIANESS_Pos            SCB_AIRCR_ENDIANNESS_Pos

#define SCB_AIRCR_ENDIANESS_Msk            SCB_AIRCR_ENDIANNESS_Msk



/* deprecated, CMSIS_5 backward compatibility */

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

        uint32_t RESERVED0[1U];

  __IOM uint32_t DAUTHCTRL;

  __IOM uint32_t DSCSR;

} CoreDebug_Type;



/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         DCB_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Msk         DCB_DHCSR_DBGKEY_Msk



#define CoreDebug_DHCSR_S_RESTART_ST_Pos   DCB_DHCSR_S_RESTART_ST_Pos

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   DCB_DHCSR_S_RESTART_ST_Msk



#define CoreDebug_DHCSR_S_RESET_ST_Pos     DCB_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Msk     DCB_DHCSR_S_RESET_ST_Msk



#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    DCB_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    DCB_DHCSR_S_RETIRE_ST_Msk



#define CoreDebug_DHCSR_S_LOCKUP_Pos       DCB_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Msk       DCB_DHCSR_S_LOCKUP_Msk



#define CoreDebug_DHCSR_S_SLEEP_Pos        DCB_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Msk        DCB_DHCSR_S_SLEEP_Msk



#define CoreDebug_DHCSR_S_HALT_Pos         DCB_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Msk         DCB_DHCSR_S_HALT_Msk



#define CoreDebug_DHCSR_S_REGRDY_Pos       DCB_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Msk       DCB_DHCSR_S_REGRDY_Msk



#define CoreDebug_DHCSR_C_MASKINTS_Pos     DCB_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Msk     DCB_DHCSR_C_MASKINTS_Msk



#define CoreDebug_DHCSR_C_STEP_Pos         DCB_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Msk         DCB_DHCSR_C_STEP_Msk



#define CoreDebug_DHCSR_C_HALT_Pos         DCB_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Msk         DCB_DHCSR_C_HALT_Msk



#define CoreDebug_DHCSR_C_DEBUGEN_Pos      DCB_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      DCB_DHCSR_C_DEBUGEN_Msk



/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         DCB_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Msk         DCB_DCRSR_REGWnR_Msk



#define CoreDebug_DCRSR_REGSEL_Pos         DCB_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Msk         DCB_DCRSR_REGSEL_Msk



/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_DWTENA_Pos         DCB_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_DWTENA_Msk         DCB_DEMCR_TRCENA_Msk



#define CoreDebug_DEMCR_VC_HARDERR_Pos     DCB_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Msk     DCB_DEMCR_VC_HARDERR_Msk



#define CoreDebug_DEMCR_VC_CORERESET_Pos   DCB_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Msk   DCB_DEMCR_VC_CORERESET_Msk



/* Debug Authentication Control Register Definitions */

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk



#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos  DCB_DAUTHCTRL_INTSPIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  DCB_DAUTHCTRL_INTSPIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos  DCB_DAUTHCTRL_SPIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  DCB_DAUTHCTRL_SPIDENSEL_Msk



/* Debug Security Control and Status Register Definitions */

#define CoreDebug_DSCSR_CDS_Pos            DCB_DSCSR_CDS_Pos

#define CoreDebug_DSCSR_CDS_Msk            DCB_DSCSR_CDS_Msk



#define CoreDebug_DSCSR_SBRSEL_Pos         DCB_DSCSR_SBRSEL_Pos

#define CoreDebug_DSCSR_SBRSEL_Msk         DCB_DSCSR_SBRSEL_Msk



#define CoreDebug_DSCSR_SBRSELEN_Pos       DCB_DSCSR_SBRSELEN_Pos

#define CoreDebug_DSCSR_SBRSELEN_Msk       DCB_DSCSR_SBRSELEN_Msk



  #define CoreDebug           ((CoreDebug_Type *)     DCB_BASE)

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

  #define CoreDebug_NS        ((CoreDebug_Type *)     DCB_BASE_NS)

#endif



/*@} */

CMSIS/Core/Include/core_cm3.h

+95 −0
Original line number Diff line number Diff line
@@ -1407,6 +1407,101 @@ typedef struct 
#define SCB_AIRCR_ENDIANESS_Pos            SCB_AIRCR_ENDIANNESS_Pos

#define SCB_AIRCR_ENDIANESS_Msk            SCB_AIRCR_ENDIANNESS_Msk



/* deprecated, CMSIS_5 backward compatibility */

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

} CoreDebug_Type;



/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         DCB_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Msk         DCB_DHCSR_DBGKEY_Msk



#define CoreDebug_DHCSR_S_RESET_ST_Pos     DCB_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Msk     DCB_DHCSR_S_RESET_ST_Msk



#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    DCB_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    DCB_DHCSR_S_RETIRE_ST_Msk



#define CoreDebug_DHCSR_S_LOCKUP_Pos       DCB_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Msk       DCB_DHCSR_S_LOCKUP_Msk



#define CoreDebug_DHCSR_S_SLEEP_Pos        DCB_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Msk        DCB_DHCSR_S_SLEEP_Msk



#define CoreDebug_DHCSR_S_HALT_Pos         DCB_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Msk         DCB_DHCSR_S_HALT_Msk



#define CoreDebug_DHCSR_S_REGRDY_Pos       DCB_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Msk       DCB_DHCSR_S_REGRDY_Msk



#define CoreDebug_DHCSR_C_SNAPSTALL_Pos    DCB_DHCSR_C_SNAPSTALL_Pos

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    DCB_DHCSR_C_SNAPSTALL_Msk



#define CoreDebug_DHCSR_C_MASKINTS_Pos     DCB_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Msk     DCB_DHCSR_C_MASKINTS_Msk



#define CoreDebug_DHCSR_C_STEP_Pos         DCB_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Msk         DCB_DHCSR_C_STEP_Msk



#define CoreDebug_DHCSR_C_HALT_Pos         DCB_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Msk         DCB_DHCSR_C_HALT_Msk



#define CoreDebug_DHCSR_C_DEBUGEN_Pos      DCB_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      DCB_DHCSR_C_DEBUGEN_Msk



/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         DCB_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Msk         DCB_DCRSR_REGWnR_Msk



#define CoreDebug_DCRSR_REGSEL_Pos         DCB_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Msk         DCB_DCRSR_REGSEL_Msk



/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_TRCENA_Pos         DCB_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Msk         DCB_DEMCR_TRCENA_Msk



#define CoreDebug_DEMCR_MON_REQ_Pos        DCB_DEMCR_MON_REQ_Pos

#define CoreDebug_DEMCR_MON_REQ_Msk        DCB_DEMCR_MON_REQ_Msk



#define CoreDebug_DEMCR_MON_STEP_Pos       DCB_DEMCR_MON_STEP_Pos

#define CoreDebug_DEMCR_MON_STEP_Msk       DCB_DEMCR_MON_STEP_Msk



#define CoreDebug_DEMCR_MON_PEND_Pos       DCB_DEMCR_MON_PEND_Pos

#define CoreDebug_DEMCR_MON_PEND_Msk       DCB_DEMCR_MON_PEND_Msk



#define CoreDebug_DEMCR_MON_EN_Pos         DCB_DEMCR_MON_EN_Pos

#define CoreDebug_DEMCR_MON_EN_Msk         DCB_DEMCR_MON_EN_Msk



#define CoreDebug_DEMCR_VC_HARDERR_Pos     DCB_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Msk     DCB_DEMCR_VC_HARDERR_Msk



#define CoreDebug_DEMCR_VC_INTERR_Pos      DCB_DEMCR_VC_INTERR_Pos

#define CoreDebug_DEMCR_VC_INTERR_Msk      DCB_DEMCR_VC_INTERR_Msk



#define CoreDebug_DEMCR_VC_BUSERR_Pos      DCB_DEMCR_VC_BUSERR_Pos

#define CoreDebug_DEMCR_VC_BUSERR_Msk      DCB_DEMCR_VC_BUSERR_Msk



#define CoreDebug_DEMCR_VC_STATERR_Pos     DCB_DEMCR_VC_STATERR_Pos

#define CoreDebug_DEMCR_VC_STATERR_Msk     DCB_DEMCR_VC_STATERR_Msk



#define CoreDebug_DEMCR_VC_CHKERR_Pos      DCB_DEMCR_VC_CHKERR_Pos

#define CoreDebug_DEMCR_VC_CHKERR_Msk      DCB_DEMCR_VC_CHKERR_Msk



#define CoreDebug_DEMCR_VC_NOCPERR_Pos     DCB_DEMCR_VC_NOCPERR_Pos

#define CoreDebug_DEMCR_VC_NOCPERR_Msk     DCB_DEMCR_VC_NOCPERR_Msk



#define CoreDebug_DEMCR_VC_MMERR_Pos       DCB_DEMCR_VC_MMERR_Pos

#define CoreDebug_DEMCR_VC_MMERR_Msk       DCB_DEMCR_VC_MMERR_Msk



#define CoreDebug_DEMCR_VC_CORERESET_Pos   DCB_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Msk   DCB_DEMCR_VC_CORERESET_Msk



  #define CoreDebug           ((CoreDebug_Type *)     DCB_BASE)



/*@} */

CMSIS/Core/Include/core_cm33.h

+127 −0
Original line number Diff line number Diff line
@@ -2105,6 +2105,133 @@ typedef struct 
#define SCB_AIRCR_ENDIANESS_Pos            SCB_AIRCR_ENDIANNESS_Pos

#define SCB_AIRCR_ENDIANESS_Msk            SCB_AIRCR_ENDIANNESS_Msk



/* deprecated, CMSIS_5 backward compatibility */

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

        uint32_t RESERVED0[1U];

  __IOM uint32_t DAUTHCTRL;

  __IOM uint32_t DSCSR;

} CoreDebug_Type;



/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         DCB_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Msk         DCB_DHCSR_DBGKEY_Msk



#define CoreDebug_DHCSR_S_RESTART_ST_Pos   DCB_DHCSR_S_RESTART_ST_Pos

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   DCB_DHCSR_S_RESTART_ST_Msk



#define CoreDebug_DHCSR_S_RESET_ST_Pos     DCB_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Msk     DCB_DHCSR_S_RESET_ST_Msk



#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    DCB_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    DCB_DHCSR_S_RETIRE_ST_Msk



#define CoreDebug_DHCSR_S_LOCKUP_Pos       DCB_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Msk       DCB_DHCSR_S_LOCKUP_Msk



#define CoreDebug_DHCSR_S_SLEEP_Pos        DCB_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Msk        DCB_DHCSR_S_SLEEP_Msk



#define CoreDebug_DHCSR_S_HALT_Pos         DCB_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Msk         DCB_DHCSR_S_HALT_Msk



#define CoreDebug_DHCSR_S_REGRDY_Pos       DCB_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Msk       DCB_DHCSR_S_REGRDY_Msk



#define CoreDebug_DHCSR_C_SNAPSTALL_Pos    DCB_DHCSR_C_SNAPSTALL_Pos

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    DCB_DHCSR_C_SNAPSTALL_Msk



#define CoreDebug_DHCSR_C_MASKINTS_Pos     DCB_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Msk     DCB_DHCSR_C_MASKINTS_Msk



#define CoreDebug_DHCSR_C_STEP_Pos         DCB_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Msk         DCB_DHCSR_C_STEP_Msk



#define CoreDebug_DHCSR_C_HALT_Pos         DCB_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Msk         DCB_DHCSR_C_HALT_Msk



#define CoreDebug_DHCSR_C_DEBUGEN_Pos      DCB_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      DCB_DHCSR_C_DEBUGEN_Msk



/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         DCB_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Msk         DCB_DCRSR_REGWnR_Msk



#define CoreDebug_DCRSR_REGSEL_Pos         DCB_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Msk         DCB_DCRSR_REGSEL_Msk



/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_TRCENA_Pos         DCB_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Msk         DCB_DEMCR_TRCENA_Msk



#define CoreDebug_DEMCR_MON_REQ_Pos        DCB_DEMCR_MON_REQ_Pos

#define CoreDebug_DEMCR_MON_REQ_Msk        DCB_DEMCR_MON_REQ_Msk



#define CoreDebug_DEMCR_MON_STEP_Pos       DCB_DEMCR_MON_STEP_Pos

#define CoreDebug_DEMCR_MON_STEP_Msk       DCB_DEMCR_MON_STEP_Msk



#define CoreDebug_DEMCR_MON_PEND_Pos       DCB_DEMCR_MON_PEND_Pos

#define CoreDebug_DEMCR_MON_PEND_Msk       DCB_DEMCR_MON_PEND_Msk



#define CoreDebug_DEMCR_MON_EN_Pos         DCB_DEMCR_MON_EN_Pos

#define CoreDebug_DEMCR_MON_EN_Msk         DCB_DEMCR_MON_EN_Msk



#define CoreDebug_DEMCR_VC_HARDERR_Pos     DCB_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Msk     DCB_DEMCR_VC_HARDERR_Msk



#define CoreDebug_DEMCR_VC_INTERR_Pos      DCB_DEMCR_VC_INTERR_Pos

#define CoreDebug_DEMCR_VC_INTERR_Msk      DCB_DEMCR_VC_INTERR_Msk



#define CoreDebug_DEMCR_VC_BUSERR_Pos      DCB_DEMCR_VC_BUSERR_Pos

#define CoreDebug_DEMCR_VC_BUSERR_Msk      DCB_DEMCR_VC_BUSERR_Msk



#define CoreDebug_DEMCR_VC_STATERR_Pos     DCB_DEMCR_VC_STATERR_Pos

#define CoreDebug_DEMCR_VC_STATERR_Msk     DCB_DEMCR_VC_STATERR_Msk



#define CoreDebug_DEMCR_VC_CHKERR_Pos      DCB_DEMCR_VC_CHKERR_Pos

#define CoreDebug_DEMCR_VC_CHKERR_Msk      DCB_DEMCR_VC_CHKERR_Msk



#define CoreDebug_DEMCR_VC_NOCPERR_Pos     DCB_DEMCR_VC_NOCPERR_Pos

#define CoreDebug_DEMCR_VC_NOCPERR_Msk     DCB_DEMCR_VC_NOCPERR_Msk



#define CoreDebug_DEMCR_VC_MMERR_Pos       DCB_DEMCR_VC_MMERR_Pos

#define CoreDebug_DEMCR_VC_MMERR_Msk       DCB_DEMCR_VC_MMERR_Msk



#define CoreDebug_DEMCR_VC_CORERESET_Pos   DCB_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Msk   DCB_DEMCR_VC_CORERESET_Msk



/* Debug Authentication Control Register Definitions */

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk



#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos  DCB_DAUTHCTRL_INTSPIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  DCB_DAUTHCTRL_INTSPIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos  DCB_DAUTHCTRL_SPIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  DCB_DAUTHCTRL_SPIDENSEL_Msk



/* Debug Security Control and Status Register Definitions */

#define CoreDebug_DSCSR_CDS_Pos            DCB_DSCSR_CDS_Pos

#define CoreDebug_DSCSR_CDS_Msk            DCB_DSCSR_CDS_Msk



#define CoreDebug_DSCSR_SBRSEL_Pos         DCB_DSCSR_SBRSEL_Pos

#define CoreDebug_DSCSR_SBRSEL_Msk         DCB_DSCSR_SBRSEL_Msk



#define CoreDebug_DSCSR_SBRSELEN_Pos       DCB_DSCSR_SBRSELEN_Pos

#define CoreDebug_DSCSR_SBRSELEN_Msk       DCB_DSCSR_SBRSELEN_Msk



  #define CoreDebug           ((CoreDebug_Type *)     DCB_BASE)

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

  #define CoreDebug_NS        ((CoreDebug_Type *)     DCB_BASE_NS)

#endif



/*@} */

CMSIS/Core/Include/core_cm35p.h

+127 −0
Original line number Diff line number Diff line
@@ -2105,6 +2105,133 @@ typedef struct 
#define SCB_AIRCR_ENDIANESS_Pos            SCB_AIRCR_ENDIANNESS_Pos

#define SCB_AIRCR_ENDIANESS_Msk            SCB_AIRCR_ENDIANNESS_Msk



/* deprecated, CMSIS_5 backward compatibility */

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

        uint32_t RESERVED0[1U];

  __IOM uint32_t DAUTHCTRL;

  __IOM uint32_t DSCSR;

} CoreDebug_Type;



/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         DCB_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Msk         DCB_DHCSR_DBGKEY_Msk



#define CoreDebug_DHCSR_S_RESTART_ST_Pos   DCB_DHCSR_S_RESTART_ST_Pos

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   DCB_DHCSR_S_RESTART_ST_Msk



#define CoreDebug_DHCSR_S_RESET_ST_Pos     DCB_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Msk     DCB_DHCSR_S_RESET_ST_Msk



#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    DCB_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    DCB_DHCSR_S_RETIRE_ST_Msk



#define CoreDebug_DHCSR_S_LOCKUP_Pos       DCB_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Msk       DCB_DHCSR_S_LOCKUP_Msk



#define CoreDebug_DHCSR_S_SLEEP_Pos        DCB_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Msk        DCB_DHCSR_S_SLEEP_Msk



#define CoreDebug_DHCSR_S_HALT_Pos         DCB_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Msk         DCB_DHCSR_S_HALT_Msk



#define CoreDebug_DHCSR_S_REGRDY_Pos       DCB_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Msk       DCB_DHCSR_S_REGRDY_Msk



#define CoreDebug_DHCSR_C_SNAPSTALL_Pos    DCB_DHCSR_C_SNAPSTALL_Pos

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    DCB_DHCSR_C_SNAPSTALL_Msk



#define CoreDebug_DHCSR_C_MASKINTS_Pos     DCB_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Msk     DCB_DHCSR_C_MASKINTS_Msk



#define CoreDebug_DHCSR_C_STEP_Pos         DCB_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Msk         DCB_DHCSR_C_STEP_Msk



#define CoreDebug_DHCSR_C_HALT_Pos         DCB_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Msk         DCB_DHCSR_C_HALT_Msk



#define CoreDebug_DHCSR_C_DEBUGEN_Pos      DCB_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      DCB_DHCSR_C_DEBUGEN_Msk



/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         DCB_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Msk         DCB_DCRSR_REGWnR_Msk



#define CoreDebug_DCRSR_REGSEL_Pos         DCB_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Msk         DCB_DCRSR_REGSEL_Msk



/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_TRCENA_Pos         DCB_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Msk         DCB_DEMCR_TRCENA_Msk



#define CoreDebug_DEMCR_MON_REQ_Pos        DCB_DEMCR_MON_REQ_Pos

#define CoreDebug_DEMCR_MON_REQ_Msk        DCB_DEMCR_MON_REQ_Msk



#define CoreDebug_DEMCR_MON_STEP_Pos       DCB_DEMCR_MON_STEP_Pos

#define CoreDebug_DEMCR_MON_STEP_Msk       DCB_DEMCR_MON_STEP_Msk



#define CoreDebug_DEMCR_MON_PEND_Pos       DCB_DEMCR_MON_PEND_Pos

#define CoreDebug_DEMCR_MON_PEND_Msk       DCB_DEMCR_MON_PEND_Msk



#define CoreDebug_DEMCR_MON_EN_Pos         DCB_DEMCR_MON_EN_Pos

#define CoreDebug_DEMCR_MON_EN_Msk         DCB_DEMCR_MON_EN_Msk



#define CoreDebug_DEMCR_VC_HARDERR_Pos     DCB_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Msk     DCB_DEMCR_VC_HARDERR_Msk



#define CoreDebug_DEMCR_VC_INTERR_Pos      DCB_DEMCR_VC_INTERR_Pos

#define CoreDebug_DEMCR_VC_INTERR_Msk      DCB_DEMCR_VC_INTERR_Msk



#define CoreDebug_DEMCR_VC_BUSERR_Pos      DCB_DEMCR_VC_BUSERR_Pos

#define CoreDebug_DEMCR_VC_BUSERR_Msk      DCB_DEMCR_VC_BUSERR_Msk



#define CoreDebug_DEMCR_VC_STATERR_Pos     DCB_DEMCR_VC_STATERR_Pos

#define CoreDebug_DEMCR_VC_STATERR_Msk     DCB_DEMCR_VC_STATERR_Msk



#define CoreDebug_DEMCR_VC_CHKERR_Pos      DCB_DEMCR_VC_CHKERR_Pos

#define CoreDebug_DEMCR_VC_CHKERR_Msk      DCB_DEMCR_VC_CHKERR_Msk



#define CoreDebug_DEMCR_VC_NOCPERR_Pos     DCB_DEMCR_VC_NOCPERR_Pos

#define CoreDebug_DEMCR_VC_NOCPERR_Msk     DCB_DEMCR_VC_NOCPERR_Msk



#define CoreDebug_DEMCR_VC_MMERR_Pos       DCB_DEMCR_VC_MMERR_Pos

#define CoreDebug_DEMCR_VC_MMERR_Msk       DCB_DEMCR_VC_MMERR_Msk



#define CoreDebug_DEMCR_VC_CORERESET_Pos   DCB_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Msk   DCB_DEMCR_VC_CORERESET_Msk



/* Debug Authentication Control Register Definitions */

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk



#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos  DCB_DAUTHCTRL_INTSPIDEN_Pos

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  DCB_DAUTHCTRL_INTSPIDEN_Msk



#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos  DCB_DAUTHCTRL_SPIDENSEL_Pos

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  DCB_DAUTHCTRL_SPIDENSEL_Msk



/* Debug Security Control and Status Register Definitions */

#define CoreDebug_DSCSR_CDS_Pos            DCB_DSCSR_CDS_Pos

#define CoreDebug_DSCSR_CDS_Msk            DCB_DSCSR_CDS_Msk



#define CoreDebug_DSCSR_SBRSEL_Pos         DCB_DSCSR_SBRSEL_Pos

#define CoreDebug_DSCSR_SBRSEL_Msk         DCB_DSCSR_SBRSEL_Msk



#define CoreDebug_DSCSR_SBRSELEN_Pos       DCB_DSCSR_SBRSELEN_Pos

#define CoreDebug_DSCSR_SBRSELEN_Msk       DCB_DSCSR_SBRSELEN_Msk



  #define CoreDebug           ((CoreDebug_Type *)     DCB_BASE)

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

  #define CoreDebug_NS        ((CoreDebug_Type *)     DCB_BASE_NS)

#endif



/*@} */

CMSIS/Core/Include/core_cm4.h

+95 −0
Original line number Diff line number Diff line
@@ -1586,6 +1586,101 @@ typedef struct 
#define SCB_AIRCR_ENDIANESS_Pos            SCB_AIRCR_ENDIANNESS_Pos

#define SCB_AIRCR_ENDIANESS_Msk            SCB_AIRCR_ENDIANNESS_Msk



/* deprecated, CMSIS_5 backward compatibility */

typedef struct

{

  __IOM uint32_t DHCSR;

  __OM  uint32_t DCRSR;

  __IOM uint32_t DCRDR;

  __IOM uint32_t DEMCR;

} CoreDebug_Type;



/* Debug Halting Control and Status Register Definitions */

#define CoreDebug_DHCSR_DBGKEY_Pos         DCB_DHCSR_DBGKEY_Pos

#define CoreDebug_DHCSR_DBGKEY_Msk         DCB_DHCSR_DBGKEY_Msk



#define CoreDebug_DHCSR_S_RESET_ST_Pos     DCB_DHCSR_S_RESET_ST_Pos

#define CoreDebug_DHCSR_S_RESET_ST_Msk     DCB_DHCSR_S_RESET_ST_Msk



#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    DCB_DHCSR_S_RETIRE_ST_Pos

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    DCB_DHCSR_S_RETIRE_ST_Msk



#define CoreDebug_DHCSR_S_LOCKUP_Pos       DCB_DHCSR_S_LOCKUP_Pos

#define CoreDebug_DHCSR_S_LOCKUP_Msk       DCB_DHCSR_S_LOCKUP_Msk



#define CoreDebug_DHCSR_S_SLEEP_Pos        DCB_DHCSR_S_SLEEP_Pos

#define CoreDebug_DHCSR_S_SLEEP_Msk        DCB_DHCSR_S_SLEEP_Msk



#define CoreDebug_DHCSR_S_HALT_Pos         DCB_DHCSR_S_HALT_Pos

#define CoreDebug_DHCSR_S_HALT_Msk         DCB_DHCSR_S_HALT_Msk



#define CoreDebug_DHCSR_S_REGRDY_Pos       DCB_DHCSR_S_REGRDY_Pos

#define CoreDebug_DHCSR_S_REGRDY_Msk       DCB_DHCSR_S_REGRDY_Msk



#define CoreDebug_DHCSR_C_SNAPSTALL_Pos    DCB_DHCSR_C_SNAPSTALL_Pos

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    DCB_DHCSR_C_SNAPSTALL_Msk



#define CoreDebug_DHCSR_C_MASKINTS_Pos     DCB_DHCSR_C_MASKINTS_Pos

#define CoreDebug_DHCSR_C_MASKINTS_Msk     DCB_DHCSR_C_MASKINTS_Msk



#define CoreDebug_DHCSR_C_STEP_Pos         DCB_DHCSR_C_STEP_Pos

#define CoreDebug_DHCSR_C_STEP_Msk         DCB_DHCSR_C_STEP_Msk



#define CoreDebug_DHCSR_C_HALT_Pos         DCB_DHCSR_C_HALT_Pos

#define CoreDebug_DHCSR_C_HALT_Msk         DCB_DHCSR_C_HALT_Msk



#define CoreDebug_DHCSR_C_DEBUGEN_Pos      DCB_DHCSR_C_DEBUGEN_Pos

#define CoreDebug_DHCSR_C_DEBUGEN_Msk      DCB_DHCSR_C_DEBUGEN_Msk



/* Debug Core Register Selector Register Definitions */

#define CoreDebug_DCRSR_REGWnR_Pos         DCB_DCRSR_REGWnR_Pos

#define CoreDebug_DCRSR_REGWnR_Msk         DCB_DCRSR_REGWnR_Msk



#define CoreDebug_DCRSR_REGSEL_Pos         DCB_DCRSR_REGSEL_Pos

#define CoreDebug_DCRSR_REGSEL_Msk         DCB_DCRSR_REGSEL_Msk



/* Debug Exception and Monitor Control Register Definitions */

#define CoreDebug_DEMCR_TRCENA_Pos         DCB_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Msk         DCB_DEMCR_TRCENA_Msk



#define CoreDebug_DEMCR_MON_REQ_Pos        DCB_DEMCR_MON_REQ_Pos

#define CoreDebug_DEMCR_MON_REQ_Msk        DCB_DEMCR_MON_REQ_Msk



#define CoreDebug_DEMCR_MON_STEP_Pos       DCB_DEMCR_MON_STEP_Pos

#define CoreDebug_DEMCR_MON_STEP_Msk       DCB_DEMCR_MON_STEP_Msk



#define CoreDebug_DEMCR_MON_PEND_Pos       DCB_DEMCR_MON_PEND_Pos

#define CoreDebug_DEMCR_MON_PEND_Msk       DCB_DEMCR_MON_PEND_Msk



#define CoreDebug_DEMCR_MON_EN_Pos         DCB_DEMCR_MON_EN_Pos

#define CoreDebug_DEMCR_MON_EN_Msk         DCB_DEMCR_MON_EN_Msk



#define CoreDebug_DEMCR_VC_HARDERR_Pos     DCB_DEMCR_VC_HARDERR_Pos

#define CoreDebug_DEMCR_VC_HARDERR_Msk     DCB_DEMCR_VC_HARDERR_Msk



#define CoreDebug_DEMCR_VC_INTERR_Pos      DCB_DEMCR_VC_INTERR_Pos

#define CoreDebug_DEMCR_VC_INTERR_Msk      DCB_DEMCR_VC_INTERR_Msk



#define CoreDebug_DEMCR_VC_BUSERR_Pos      DCB_DEMCR_VC_BUSERR_Pos

#define CoreDebug_DEMCR_VC_BUSERR_Msk      DCB_DEMCR_VC_BUSERR_Msk



#define CoreDebug_DEMCR_VC_STATERR_Pos     DCB_DEMCR_VC_STATERR_Pos

#define CoreDebug_DEMCR_VC_STATERR_Msk     DCB_DEMCR_VC_STATERR_Msk



#define CoreDebug_DEMCR_VC_CHKERR_Pos      DCB_DEMCR_VC_CHKERR_Pos

#define CoreDebug_DEMCR_VC_CHKERR_Msk      DCB_DEMCR_VC_CHKERR_Msk



#define CoreDebug_DEMCR_VC_NOCPERR_Pos     DCB_DEMCR_VC_NOCPERR_Pos

#define CoreDebug_DEMCR_VC_NOCPERR_Msk     DCB_DEMCR_VC_NOCPERR_Msk



#define CoreDebug_DEMCR_VC_MMERR_Pos       DCB_DEMCR_VC_MMERR_Pos

#define CoreDebug_DEMCR_VC_MMERR_Msk       DCB_DEMCR_VC_MMERR_Msk



#define CoreDebug_DEMCR_VC_CORERESET_Pos   DCB_DEMCR_VC_CORERESET_Pos

#define CoreDebug_DEMCR_VC_CORERESET_Msk   DCB_DEMCR_VC_CORERESET_Msk



  #define CoreDebug           ((CoreDebug_Type *)     DCB_BASE)



/*@} */

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