Commit fea79619 authored by Stephanos Ioannidis's avatar Stephanos Ioannidis Committed by Anas Nashif
Browse files

Core-A: Import CMSIS-Core(A) 1.2.1 (CMSIS 5.8.0) 

This commit imports the CMSIS-Core(A) 1.2.1, which is part of the
CMSIS 5.8.0 release.

Origin: CMSIS_5
License: Apache-2.0
URL: https://github.com/ARM-software/CMSIS_5/tree/5.8.0


commit: 13b9f72f212688d2306d0d085d87cbb4bf9e5d3f
Purpose: Provide a hardware interface to the Arm Cortex-A architecture
Maintained-by: External

Signed-off-by: default avatarStephanos Ioannidis <root@stephanos.io>
parent 496b2a6d

CMSIS/Core_A/Include/cmsis_armcc.h

+31 −3
Original line number Diff line number Diff line 
/**************************************************************************//**

 * @file     cmsis_armcc.h

 * @brief    CMSIS compiler specific macros, functions, instructions

 * @version  V1.0.4

 * @date     30. July 2019

 * @version  V1.0.5

 * @date     05. May 2021

 ******************************************************************************/

/*

 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *
@@ -296,6 +296,34 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in 


/* ###########################  Core Function Access  ########################### */



/**

  \brief   Enable IRQ Interrupts

  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

/* intrinsic void __enable_irq(); */



/**

  \brief   Disable IRQ Interrupts

  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

  Can only be executed in Privileged modes.

 */

/* intrinsic void __disable_irq(void); */



/**

  \brief   Enable FIQ

  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

#define __enable_fault_irq                __enable_fiq



/**

  \brief   Disable FIQ

  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

#define __disable_fault_irq               __disable_fiq



/**

  \brief   Get FPSCR (Floating Point Status/Control)

  \return               Floating Point Status/Control register value

CMSIS/Core_A/Include/cmsis_armclang.h

+48 −12
Original line number Diff line number Diff line 
/**************************************************************************//**

 * @file     cmsis_armclang.h

 * @brief    CMSIS compiler specific macros, functions, instructions

 * @version  V1.2.0

 * @date     05. August 2019

 * @version  V1.2.1

 * @date     05. May 2021

 ******************************************************************************/

/*

 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *
@@ -27,10 +27,6 @@ 


#pragma clang system_header   /* treat file as system include file */



#ifndef __ARM_COMPAT_H

#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */

#endif



/* CMSIS compiler specific defines */

#ifndef   __ASM

  #define __ASM                                  __asm
@@ -372,6 +368,46 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) 


/* ###########################  Core Function Access  ########################### */



/**

  \brief   Enable IRQ Interrupts

  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __enable_irq(void)

{

  __ASM volatile ("cpsie i" : : : "memory");

}



/**

  \brief   Disable IRQ Interrupts

  \details Disables IRQ interrupts by setting the I-bit in the CPSR.

  Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __disable_irq(void)

{

  __ASM volatile ("cpsid i" : : : "memory");

}



/**

  \brief   Enable FIQ

  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __enable_fault_irq(void)

{

  __ASM volatile ("cpsie f" : : : "memory");

}



/**

  \brief   Disable FIQ

  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __disable_fault_irq(void)

{

  __ASM volatile ("cpsid f" : : : "memory");

}



/**

  \brief   Get FPSCR

  \details Returns the current value of the Floating Point Status/Control register.
@@ -423,7 +459,7 @@ __STATIC_FORCEINLINE void __set_mode(uint32_t mode) 
/** \brief  Get Stack Pointer

    \return Stack Pointer value

 */

__STATIC_FORCEINLINE uint32_t __get_SP()

__STATIC_FORCEINLINE uint32_t __get_SP(void)

{

  uint32_t result;

  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
@@ -441,7 +477,7 @@ __STATIC_FORCEINLINE void __set_SP(uint32_t stack) 
/** \brief  Get USR/SYS Stack Pointer

    \return USR/SYS Stack Pointer value

 */

__STATIC_FORCEINLINE uint32_t __get_SP_usr()

__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)

{

  uint32_t cpsr;

  uint32_t result;
@@ -546,7 +582,7 @@ __STATIC_INLINE void __FPU_Enable(void) 
    "        VMOV    D14,R2,R2         \n"

    "        VMOV    D15,R2,R2         \n"



#if __ARM_NEON == 1

#if (defined(__ARM_NEON) && (__ARM_NEON == 1))

    //Initialise D32 registers to 0

    "        VMOV    D16,R2,R2         \n"

    "        VMOV    D17,R2,R2         \n"

CMSIS/Core_A/Include/cmsis_gcc.h

+38 −18
Original line number Diff line number Diff line 
/**************************************************************************//**

 * @file     cmsis_gcc.h

 * @brief    CMSIS compiler specific macros, functions, instructions

 * @version  V1.3.0

 * @date     17. December 2019

 * @version  V1.3.1

 * @date     05. May 2021

 ******************************************************************************/

/*

 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.

 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *
@@ -37,7 +37,6 @@ 
#endif



/* CMSIS compiler specific defines */



#ifndef   __ASM

  #define __ASM                                  __asm

#endif
@@ -436,7 +435,8 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)

{

  op2 %= 32U;

  if (op2 == 0U) {

  if (op2 == 0U)

  {

    return op1;

  }

  return (op1 >> op2) | (op1 << (32U - op2));
@@ -674,6 +674,26 @@ __STATIC_FORCEINLINE void __disable_irq(void) 
  __ASM volatile ("cpsid i" : : : "memory");

}



/**

  \brief   Enable FIQ

  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __enable_fault_irq(void)

{

  __ASM volatile ("cpsie f" : : : "memory");

}



/**

  \brief   Disable FIQ

  \details Disables FIQ interrupts by setting the F-bit in the CPSR.

           Can only be executed in Privileged modes.

 */

__STATIC_FORCEINLINE void __disable_fault_irq(void)

{

  __ASM volatile ("cpsid f" : : : "memory");

}



/**

  \brief   Get FPSCR

  \details Returns the current value of the Floating Point Status/Control register.
@@ -810,7 +830,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPEXC(void) 
{

#if (__FPU_PRESENT == 1)

  uint32_t result;

  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );

  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");

  return(result);

#else

  return(0);

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