Commit 496b2a6d authored by Stephanos Ioannidis's avatar Stephanos Ioannidis Committed by Anas Nashif
Browse files

Core-M: Import CMSIS-Core(M) 5.5.0 (CMSIS 5.8.0) 

This commit imports the CMSIS-Core(M) 5.5.0, which is part of the
CMSIS 5.8.0 release.

Origin: CMSIS_5
License: Apache-2.0
URL: https://github.com/ARM-software/CMSIS_5/tree/5.8.0


commit: 13b9f72f212688d2306d0d085d87cbb4bf9e5d3f
Purpose: Provide a hardware interface to the Arm Cortex-M architecture
Maintained-by: External

Signed-off-by: default avatarStephanos Ioannidis <root@stephanos.io>
parent c3bd2094

CMSIS/Core/Include/cachel1_armv7.h

+14 −14
Original line number Diff line number Diff line 
/******************************************************************************

 * @file     cachel1_armv7.h

 * @brief    CMSIS Level 1 Cache API for Armv7-M and later

 * @version  V1.0.0

 * @date     03. March 2020

 * @version  V1.0.1

 * @date     19. April 2021

 ******************************************************************************/

/*

 * Copyright (c) 2020 Arm Limited. All rights reserved.

 * Copyright (c) 2020-2021 Arm Limited. All rights reserved.

 *

 * SPDX-License-Identifier: Apache-2.0

 *
@@ -112,7 +112,7 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) 
  \param[in]   addr    address

  \param[in]   isize   size of memory block (in number of bytes)

*/

__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)

__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)

{

  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)

    if ( isize > 0 ) {
@@ -325,7 +325,7 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) 
  \param[in]   addr    address

  \param[in]   dsize   size of memory block (in number of bytes)

*/

__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)

__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {
@@ -355,7 +355,7 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz 
  \param[in]   addr    address

  \param[in]   dsize   size of memory block (in number of bytes)

*/

__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)

__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {
@@ -385,7 +385,7 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize 
  \param[in]   addr    address (aligned to 32-byte boundary)

  \param[in]   dsize   size of memory block (in number of bytes)

*/

__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)

__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)

{

  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)

    if ( dsize > 0 ) {

CMSIS/Core/Include/cmsis_armcc.h

+403 −400

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CMSIS/Core/Include/cmsis_armclang.h

+846 −810

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CMSIS/Core/Include/cmsis_armclang_ltm.h

+825 −790

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CMSIS/Core/Include/cmsis_gcc.h

+951 −917

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