Commit fffde96e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v5.9-next-dts32' of... 

Merge tag 'v5.9-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt2701:
- add jpeg enconder node
mt7623:
- refactor dts and add hdmi support

* tag 'v5.9-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm: dts: mt7623: add missing pause for switchport
  arm: dts: mt7623: add lima related regulator
  arm: dts: mt7623: add display subsystem related device nodes
  arm: dts: mt7623: move display nodes to separate mt7623n.dtsi
  arm: dts: mt2701: Add jpeg enc device tree node

Link: https://lore.kernel.org/r/641d4d47-b7ad-42dd-f7a8-e028a1f64d70@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f75ff2c7 36f0a5fc

arch/arm/boot/dts/mt2701.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -569,6 +569,19 @@ 
			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;

	};



	jpegenc: jpegenc@1500a000 {

		compatible = "mediatek,mt2701-jpgenc",

			     "mediatek,mtk-jpgenc";

		reg = <0 0x1500a000 0 0x1000>;

		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;

		clocks =  <&imgsys CLK_IMG_VENC>;

		clock-names = "jpgenc";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,

			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;

	};



	vdecsys: syscon@16000000 {

		compatible = "mediatek,mt2701-vdecsys", "syscon";

		reg = <0 0x16000000 0 0x1000>;

arch/arm/boot/dts/mt7623.dtsi

+0 −123
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
#include <dt-bindings/power/mt2701-power.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/memory/mt2701-larb-port.h>

#include <dt-bindings/reset/mt2701-resets.h>

#include <dt-bindings/thermal/thermal.h>
@@ -297,17 +296,6 @@ 
		clock-names = "system-clk", "rtc-clk";

	};



	smi_common: smi@1000c000 {

		compatible = "mediatek,mt7623-smi-common",

			     "mediatek,mt2701-smi-common";

		reg = <0 0x1000c000 0 0x1000>;

		clocks = <&infracfg CLK_INFRA_SMI>,

			 <&mmsys CLK_MM_SMI_COMMON>,

			 <&infracfg CLK_INFRA_SMI>;

		clock-names = "apb", "smi", "async";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	pwrap: pwrap@1000d000 {

		compatible = "mediatek,mt7623-pwrap",

			     "mediatek,mt2701-pwrap";
@@ -339,17 +327,6 @@ 
		reg = <0 0x10200100 0 0x1c>;

	};



	iommu: mmsys_iommu@10205000 {

		compatible = "mediatek,mt7623-m4u",

			     "mediatek,mt2701-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2>;

		#iommu-cells = <1>;

	};



	efuse: efuse@10206000 {

		compatible = "mediatek,mt7623-efuse",

			     "mediatek,mt8173-efuse";
@@ -725,94 +702,6 @@ 
		status = "disabled";

	};



	g3dsys: syscon@13000000 {

		compatible = "mediatek,mt7623-g3dsys",

			     "mediatek,mt2701-g3dsys",

			     "syscon";

		reg = <0 0x13000000 0 0x200>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	mali: gpu@13040000 {

		compatible = "mediatek,mt7623-mali", "arm,mali-450";

		reg = <0 0x13040000 0 0x30000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",

				  "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",

				  "pp";

		clocks = <&topckgen CLK_TOP_MMPLL>,

			 <&g3dsys CLK_G3DSYS_CORE>;

		clock-names = "bus", "core";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;

		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;

	};



	mmsys: syscon@14000000 {

		compatible = "mediatek,mt7623-mmsys",

			     "mediatek,mt2701-mmsys",

			     "syscon";

		reg = <0 0x14000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb0: larb@14010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <0>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	imgsys: syscon@15000000 {

		compatible = "mediatek,mt7623-imgsys",

			     "mediatek,mt2701-imgsys",

			     "syscon";

		reg = <0 0x15000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb2: larb@15001000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x15001000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <2>;

		clocks = <&imgsys CLK_IMG_SMI_COMM>,

			 <&imgsys CLK_IMG_SMI_COMM>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

	};



	jpegdec: jpegdec@15004000 {

		compatible = "mediatek,mt7623-jpgdec",

			     "mediatek,mt2701-jpgdec";

		reg = <0 0x15004000 0 0x1000>;

		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;

		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,

			  <&imgsys CLK_IMG_JPGDEC>;

		clock-names = "jpgdec-smi",

			      "jpgdec";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,

			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;

	};



	vdecsys: syscon@16000000 {

		compatible = "mediatek,mt7623-vdecsys",

			     "mediatek,mt2701-vdecsys",
@@ -821,18 +710,6 @@ 
		#clock-cells = <1>;

	};



	larb1: larb@16010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <1>;

		clocks = <&vdecsys CLK_VDEC_CKGEN>,

			 <&vdecsys CLK_VDEC_LARB>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;

	};



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",

			     "mediatek,mt2701-hifsys",

arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts

+86 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 


/dts-v1/;

#include <dt-bindings/input/input.h>

#include "mt7623.dtsi"

#include "mt7623n.dtsi"

#include "mt6323.dtsi"



/ {
@@ -21,6 +21,19 @@ 
		stdout-path = "serial2:115200n8";

	};



	connector {

		compatible = "hdmi-connector";

		label = "hdmi";

		type = "d";

		ddc-i2c-bus = <&hdmiddc0>;



		port {

			hdmi_connector_in: endpoint {

				remote-endpoint = <&hdmi0_out>;

			};

		};

	};



	cpus {

		cpu@0 {

			proc-supply = <&mt6323_vproc_reg>;
@@ -66,6 +79,13 @@ 
		regulator-always-on;

	};



	reg_vgpu: fixedregulator@0 {

		compatible = "regulator-fixed";

		regulator-name = "vdd_fixed_vgpu";

		regulator-min-microvolt = <1150000>;

		regulator-max-microvolt = <1150000>;

	};



	gpio-keys {

		compatible = "gpio-keys";

		pinctrl-names = "default";
@@ -114,10 +134,18 @@ 
	};

};



&bls {

	status = "okay";

};



&btif {

	status = "okay";

};



&cec {

	status = "okay";

};



&cir {

	pinctrl-names = "default";

	pinctrl-0 = <&cir_pins_a>;
@@ -128,6 +156,21 @@ 
	status = "okay";

};



&dpi0 {

	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			dpi0_out: endpoint {

				remote-endpoint = <&hdmi0_in>;

			};

		};

	};

};



&eth {

	status = "okay";
@@ -192,11 +235,48 @@ 
					fixed-link {

						speed = <1000>;

						full-duplex;

						pause;

					};

				};

			};

		};

	};

};



&hdmi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&hdmi_pins_a>;

	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			hdmi0_in: endpoint {

				remote-endpoint = <&dpi0_out>;

			};

		};



		port@1 {

			reg = <1>;

			hdmi0_out: endpoint {

				remote-endpoint = <&hdmi_connector_in>;

			};

		};

	};

};



&hdmiddc0 {

	pinctrl-names = "default";

	pinctrl-0 = <&hdmi_ddc_pins_a>;

	status = "okay";

};



&hdmi_phy {

	mediatek,ibias = <0xa>;

	mediatek,ibias_up = <0x1c>;

	status = "okay";

};



&i2c0 {
@@ -211,6 +291,11 @@ 
	status = "okay";

};



&mali {

	mali-supply = <&reg_vgpu>;

	status = "okay";

};



&mmc0 {

	pinctrl-names = "default", "state_uhs";

	pinctrl-0 = <&mmc0_pins_default>;
@@ -330,4 +415,3 @@ 
&u3phy2 {

	status = "okay";

};

arch/arm/boot/dts/mt7623n-rfb-emmc.dts

+73 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 


/dts-v1/;

#include <dt-bindings/input/input.h>

#include "mt7623.dtsi"

#include "mt7623n.dtsi"

#include "mt6323.dtsi"



/ {
@@ -24,6 +24,19 @@ 
		stdout-path = "serial2:115200n8";

	};



	connector {

		compatible = "hdmi-connector";

		label = "hdmi";

		type = "d";

		ddc-i2c-bus = <&hdmiddc0>;



		port {

			hdmi_connector_in: endpoint {

				remote-endpoint = <&hdmi0_out>;

			};

		};

	};



	cpus {

		cpu@0 {

			proc-supply = <&mt6323_vproc_reg>;
@@ -106,10 +119,18 @@ 
	};

};



&bls {

	status = "okay";

};



&btif {

	status = "okay";

};



&cec {

	status = "okay";

};



&cir {

	pinctrl-names = "default";

	pinctrl-0 = <&cir_pins_a>;
@@ -120,6 +141,21 @@ 
	status = "okay";

};



&dpi0 {

	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			dpi0_out: endpoint {

				remote-endpoint = <&hdmi0_in>;

			};

		};

	};

};



&eth {

	status = "okay";
@@ -203,6 +239,42 @@ 
	};

};



&hdmi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&hdmi_pins_a>;

	status = "okay";



	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			hdmi0_in: endpoint {

				remote-endpoint = <&dpi0_out>;

			};

		};



		port@1 {

			reg = <1>;

			hdmi0_out: endpoint {

				remote-endpoint = <&hdmi_connector_in>;

			};

		};

	};

};



&hdmiddc0 {

	pinctrl-names = "default";

	pinctrl-0 = <&hdmi_ddc_pins_a>;

	status = "okay";

};



&hdmi_phy {

	mediatek,ibias = <0xa>;

	mediatek,ibias_up = <0x1c>;

	status = "okay";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_pins_a>;

arch/arm/boot/dts/mt7623n.dtsi

0 → 100644
+306 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright © 2017-2020 MediaTek Inc.

 * Author: Sean Wang <sean.wang@mediatek.com>

 *	   Ryder Lee <ryder.lee@mediatek.com>

 *

 */



#include "mt7623.dtsi"

#include <dt-bindings/memory/mt2701-larb-port.h>



/ {

	aliases {

		rdma0 = &rdma0;

		rdma1 = &rdma1;

	};



	g3dsys: syscon@13000000 {

		compatible = "mediatek,mt7623-g3dsys",

			     "mediatek,mt2701-g3dsys",

			     "syscon";

		reg = <0 0x13000000 0 0x200>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	mali: gpu@13040000 {

		compatible = "mediatek,mt7623-mali", "arm,mali-450";

		reg = <0 0x13040000 0 0x30000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",

				  "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",

				  "pp";

		clocks = <&topckgen CLK_TOP_MMPLL>,

			 <&g3dsys CLK_G3DSYS_CORE>;

		clock-names = "bus", "core";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;

		resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;

	};



	mmsys: syscon@14000000 {

		compatible = "mediatek,mt7623-mmsys",

			     "mediatek,mt2701-mmsys",

			     "syscon";

		reg = <0 0x14000000 0 0x1000>;

		#clock-cells = <1>;

	};



	larb0: larb@14010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x14010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <0>;

		clocks = <&mmsys CLK_MM_SMI_LARB0>,

			 <&mmsys CLK_MM_SMI_LARB0>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	larb1: larb@16010000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <1>;

		clocks = <&vdecsys CLK_VDEC_CKGEN>,

			 <&vdecsys CLK_VDEC_LARB>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;

	};



	larb2: larb@15001000 {

		compatible = "mediatek,mt7623-smi-larb",

			     "mediatek,mt2701-smi-larb";

		reg = <0 0x15001000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		mediatek,larb-id = <2>;

		clocks = <&imgsys CLK_IMG_SMI_COMM>,

			 <&imgsys CLK_IMG_SMI_COMM>;

		clock-names = "apb", "smi";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

	};



	imgsys: syscon@15000000 {

		compatible = "mediatek,mt7623-imgsys",

			     "mediatek,mt2701-imgsys",

			     "syscon";

		reg = <0 0x15000000 0 0x1000>;

		#clock-cells = <1>;

	};



	iommu: mmsys_iommu@10205000 {

		compatible = "mediatek,mt7623-m4u",

			     "mediatek,mt2701-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2>;

		#iommu-cells = <1>;

	};



	jpegdec: jpegdec@15004000 {

		compatible = "mediatek,mt7623-jpgdec",

			     "mediatek,mt2701-jpgdec";

		reg = <0 0x15004000 0 0x1000>;

		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;

		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,

			  <&imgsys CLK_IMG_JPGDEC>;

		clock-names = "jpgdec-smi",

			      "jpgdec";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

		mediatek,larb = <&larb2>;

		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,

			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;

	};



	smi_common: smi@1000c000 {

		compatible = "mediatek,mt7623-smi-common",

			     "mediatek,mt2701-smi-common";

		reg = <0 0x1000c000 0 0x1000>;

		clocks = <&infracfg CLK_INFRA_SMI>,

			 <&mmsys CLK_MM_SMI_COMMON>,

			 <&infracfg CLK_INFRA_SMI>;

		clock-names = "apb", "smi", "async";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;

	};



	ovl: ovl@14007000 {

		compatible = "mediatek,mt7623-disp-ovl",

			     "mediatek,mt2701-disp-ovl";

		reg = <0 0x14007000 0 0x1000>;

		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_OVL>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;

		mediatek,larb = <&larb0>;

	};



	rdma0: rdma@14008000 {

		compatible = "mediatek,mt7623-disp-rdma",

			     "mediatek,mt2701-disp-rdma";

		reg = <0 0x14008000 0 0x1000>;

		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_RDMA>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;

		mediatek,larb = <&larb0>;

	};



	wdma@14009000 {

		compatible = "mediatek,mt7623-disp-wdma",

			     "mediatek,mt2701-disp-wdma";

		reg = <0 0x14009000 0 0x1000>;

		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_WDMA>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;

		mediatek,larb = <&larb0>;

	};



	bls: pwm@1400a000 {

		compatible = "mediatek,mt7623-disp-pwm",

			     "mediatek,mt2701-disp-pwm";

		reg = <0 0x1400a000 0 0x1000>;

		#pwm-cells = <2>;

		clocks = <&mmsys CLK_MM_MDP_BLS_26M>,

			 <&mmsys CLK_MM_DISP_BLS>;

		clock-names = "main", "mm";

		status = "disabled";

	};



	color: color@1400b000 {

		compatible = "mediatek,mt7623-disp-color",

			     "mediatek,mt2701-disp-color";

		reg = <0 0x1400b000 0 0x1000>;

		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_COLOR>;

	};



	dsi: dsi@1400c000 {

		compatible = "mediatek,mt7623-dsi",

			     "mediatek,mt2701-dsi";

		reg = <0 0x1400c000 0 0x1000>;

		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DSI_ENGINE>,

			 <&mmsys CLK_MM_DSI_DIG>,

			 <&mipi_tx0>;

		clock-names = "engine", "digital", "hs";

		phys = <&mipi_tx0>;

		phy-names = "dphy";

		status = "disabled";

	};



	mutex: mutex@1400e000 {

		compatible = "mediatek,mt7623-disp-mutex",

			     "mediatek,mt2701-disp-mutex";

		reg = <0 0x1400e000 0 0x1000>;

		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_MUTEX_32K>;

	};



	rdma1: rdma@14012000 {

		compatible = "mediatek,mt7623-disp-rdma",

			     "mediatek,mt2701-disp-rdma";

		reg = <0 0x14012000 0 0x1000>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DISP_RDMA1>;

		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;

		mediatek,larb = <&larb0>;

	};



	dpi0: dpi@14014000 {

		compatible = "mediatek,mt7623-dpi",

			     "mediatek,mt2701-dpi";

		reg = <0 0x14014000 0 0x1000>;

		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&mmsys CLK_MM_DPI1_DIGL>,

			 <&mmsys CLK_MM_DPI1_ENGINE>,

			 <&apmixedsys CLK_APMIXED_TVDPLL>;

		clock-names = "pixel", "engine", "pll";

		status = "disabled";

	};



	hdmi0: hdmi@14015000 {

		compatible = "mediatek,mt7623-hdmi",

			     "mediatek,mt2701-hdmi";

		reg = <0 0x14015000 0 0x400>;

		clocks = <&mmsys CLK_MM_HDMI_PIXEL>,

			 <&mmsys CLK_MM_HDMI_PLL>,

			 <&mmsys CLK_MM_HDMI_AUDIO>,

			 <&mmsys CLK_MM_HDMI_SPDIF>;

		clock-names = "pixel", "pll", "bclk", "spdif";

		phys = <&hdmi_phy>;

		phy-names = "hdmi";

		mediatek,syscon-hdmi = <&mmsys 0x900>;

		cec = <&cec>;

		status = "disabled";

	};



	mipi_tx0: mipi-dphy@10010000 {

		compatible = "mediatek,mt7623-mipi-tx",

			     "mediatek,mt2701-mipi-tx";

		reg = <0 0x10010000 0 0x90>;

		clocks = <&clk26m>;

		clock-output-names = "mipi_tx0_pll";

		#clock-cells = <0>;

		#phy-cells = <0>;

	};



	cec: cec@10012000 {

		compatible = "mediatek,mt7623-cec",

			     "mediatek,mt8173-cec";

		reg = <0 0x10012000 0 0xbc>;

		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_CEC>;

		status = "disabled";

	};



	hdmi_phy: phy@10209100 {

		compatible = "mediatek,mt7623-hdmi-phy",

			     "mediatek,mt2701-hdmi-phy";

		reg = <0 0x10209100 0 0x24>;

		clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;

		clock-names = "pll_ref";

		clock-output-names = "hdmitx_dig_cts";

		#clock-cells = <0>;

		#phy-cells = <0>;

		status = "disabled";

	};



	hdmiddc0: i2c@11013000 {

		compatible = "mediatek,mt7623-hdmi-ddc",

			     "mediatek,mt8173-hdmi-ddc";

		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;

		reg = <0 0x11013000 0 0x1C>;

		clocks = <&pericfg CLK_PERI_I2C3>;

		clock-names = "ddc-i2c";

		status = "disabled";

	};

};



&pio {

	hdmi_pins_a: hdmi-default {

		pins-hdmi {

			pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;

			input-enable;

			bias-pull-down;

		};

	};



	hdmi_ddc_pins_a: hdmi_ddc-default {

		pins-hdmi-ddc {

			pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,

				 <MT7623_PIN_125_GPIO125_FUNC_HDMISD>;

		};

	};

};

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