dmaengine: dw: Fix FIFO size for Intel Merrifield (ffe843b1) · Commits · 戴 / test

Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller, i.e. 512 bytes instead of 1024. Fix this by partitioning it as 64 bytes per channel. Note, in the future we might switch to 'fifo-size' property instead of hard coded value. Fixes: ("dmaengine: dw: add support of iDMA 32-bit hardware") Signed-off-by:

Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by:

Vinod Koul <vkoul@kernel.org>

drivers/dma/dw/core.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -1059,12 +1059,12 @@ static void dwc_issue_pending(struct dma_chan *chan)
		/*
		* Program FIFO size of channels.
		*
		* By default full FIFO (1024 bytes) is assigned to channel 0. Here we
		* By default full FIFO (512 bytes) is assigned to channel 0. Here we
		* slice FIFO on equal parts between channels.
		*/
		static void idma32_fifo_partition(struct dw_dma *dw)
		{
		u64 value = IDMA32C_FP_PSIZE_CH0(128) \| IDMA32C_FP_PSIZE_CH1(128) \|
		u64 value = IDMA32C_FP_PSIZE_CH0(64) \| IDMA32C_FP_PSIZE_CH1(64) \|
		IDMA32C_FP_UPDATE;
		u64 fifo_partition = 0;

		@@ -1077,7 +1077,7 @@ static void idma32_fifo_partition(struct dw_dma *dw)
		/* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
		fifo_partition \|= value << 32;

		/* Program FIFO Partition registers - 128 bytes for each channel */
		/* Program FIFO Partition registers - 64 bytes per channel */
		idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
		idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
		}

Admin message