Commit ffd3b1c8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-next 

 - Hisilicon 3670 SoC support

* clk-samsung:
  dt-bindings: clock: samsung: Add SPDX license identifiers
  clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
  clk: samsung: exynos5420: Enable PERIS clocks for suspend
  clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
  clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
  clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
  clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
  clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
  clk: samsung: exynos5420: Use generic helper for handling suspend/resume
  clk: samsung: exynos4: Use generic helper for handling suspend/resume
  clk: samsung: Add support for setting registers state before suspend
  clk: samsung: exynos5250: Use generic helper for handling suspend/resume
  clk: samsung: s5pv210: Use generic helper for handling suspend/resume
  clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
  clk: samsung: s3c2443: Use generic helper for handling suspend/resume
  clk: samsung: s3c2412: Use generic helper for handling suspend/resume
  clk: samsung: s3c2410: Use generic helper for handling suspend/resume
  clk: samsung: Remove excessive include

* clk-hisi3670:
  clk: hisilicon: Add clock driver for Hi3670 SoC
  dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk

* clk-at91-div-0:
  clk: at91: Fix division by zero in PLL recalc_rate()
parents 8a69f1d4 6df9543d c1a3308a 0f5cb0e6

Documentation/devicetree/bindings/clock/hi3670-clock.txt

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* Hisilicon Hi3670 Clock Controller



The Hi3670 clock controller generates and supplies clock to various

controllers within the Hi3670 SoC.



Required Properties:



- compatible: the compatible should be one of the following strings to

	indicate the clock controller functionality.



	- "hisilicon,hi3670-crgctrl"

	- "hisilicon,hi3670-pctrl"

	- "hisilicon,hi3670-pmuctrl"

	- "hisilicon,hi3670-sctrl"

	- "hisilicon,hi3670-iomcu"

	- "hisilicon,hi3670-media1-crg"

	- "hisilicon,hi3670-media2-crg"



- reg: physical base address of the controller and length of memory mapped

  region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes use this identifier

to specify the clock which they consume.



All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.



Examples:

	crg_ctrl: clock-controller@fff35000 {

		compatible = "hisilicon,hi3670-crgctrl", "syscon";

		reg = <0x0 0xfff35000 0x0 0x1000>;

		#clock-cells = <1>;

	};



	uart0: serial@fdf02000 {

		compatible = "arm,pl011", "arm,primecell";

		reg = <0x0 0xfdf02000 0x0 0x1000>;

		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,

			 <&crg_ctrl HI3670_PCLK>;

		clock-names = "uartclk", "apb_pclk";

	};

drivers/clk/at91/clk-pll.c

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@@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 
{

	struct clk_pll *pll = to_clk_pll(hw);



	if (!pll->div || !pll->mul)

		return 0;



	return (parent_rate / pll->div) * (pll->mul + 1);

}

drivers/clk/hisilicon/Kconfig

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@@ -21,6 +21,13 @@ config COMMON_CLK_HI3660 
	help

	  Build the clock driver for hi3660.



config COMMON_CLK_HI3670

	bool "Hi3670 Clock Driver"

	depends on ARCH_HISI || COMPILE_TEST

	default ARCH_HISI

	help

	  Build the clock driver for hi3670.



config COMMON_CLK_HI3798CV200

	tristate "Hi3798CV200 Clock Driver"

	depends on ARCH_HISI || COMPILE_TEST

drivers/clk/hisilicon/Makefile

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@@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o 
obj-$(CONFIG_COMMON_CLK_HI3516CV300)	+= crg-hi3516cv300.o

obj-$(CONFIG_COMMON_CLK_HI3519)	+= clk-hi3519.o

obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o

obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o

obj-$(CONFIG_COMMON_CLK_HI3798CV200)	+= crg-hi3798cv200.o

obj-$(CONFIG_COMMON_CLK_HI6220)	+= clk-hi6220.o

obj-$(CONFIG_RESET_HISI)	+= reset.o

drivers/clk/hisilicon/clk-hi3670.c

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