dt-bindings: spi: Convert stm32 QSPI bindings to json-schema

* STMicroelectronics Quad Serial Peripheral Interface(QSPI)

Required properties:

- compatible: should be "st,stm32f469-qspi"

- reg: the first contains the register location and length.

       the second contains the memory mapping address and length

- reg-names: should contain the reg names "qspi" "qspi_mm"

- interrupts: should contain the interrupt for the device

- clocks: the phandle of the clock needed by the QSPI controller

- A pinctrl must be defined to set pins in mode of operation for QSPI transfer

Optional properties:

- resets: must contain the phandle to the reset controller.

A spi flash (NOR/NAND) must be a child of spi node and could have some

properties. Also see jedec,spi-nor.txt.

Required properties:

- reg: chip-Select number (QSPI controller may connect 2 flashes)

- spi-max-frequency: max frequency of spi bus

Optional properties:

- spi-rx-bus-width: see ./spi-bus.txt for the description

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

Documentation/devicetree/bindings/dma/dma.txt.

- dma-names: DMA request names should include "tx" and "rx" if present.

Example:

qspi: spi@a0001000 {

	compatible = "st,stm32f469-qspi";

	reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;

	reg-names = "qspi", "qspi_mm";

	interrupts = <91>;

	resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;

	clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_qspi0>;

	flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>;

		...

	};

};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings

maintainers:

  - Christophe Kerello <christophe.kerello@st.com>

  - Patrice Chotard <patrice.chotard@st.com>

allOf:

  - $ref: "spi-controller.yaml#"

properties:

  compatible:

    const: st,stm32f469-qspi

  reg:

    items:

      - description: registers

      - description: memory mapping

  reg-names:

    items:

     - const: qspi

     - const: qspi_mm

  clocks:

    maxItems: 1

  interrupts:

    maxItems: 1

  resets:

    maxItems: 1

  dmas:

    items:

      - description: tx DMA channel

      - description: rx DMA channel

  dma-names:

    items:

      - const: tx

      - const: rx

required:

  - compatible

  - reg

  - reg-names

  - clocks

  - interrupts

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/stm32mp1-clks.h>

    #include <dt-bindings/reset/stm32mp1-resets.h>

    spi@58003000 {

      compatible = "st,stm32f469-qspi";

      reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;

      reg-names = "qspi", "qspi_mm";

      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

      dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,

             <&mdma1 22 0x10 0x100008 0x0 0x0>;

      dma-names = "tx", "rx";

      clocks = <&rcc QSPI_K>;

      resets = <&rcc QSPI_R>;

      #address-cells = <1>;

      #size-cells = <0>;

      flash@0 {

        compatible = "jedec,spi-nor";

        reg = <0>;

        spi-rx-bus-width = <4>;

        spi-max-frequency = <108000000>;

      };

    };

...