Commit ff8e0ff9 authored by Sylwester Nawrocki's avatar Sylwester Nawrocki
Browse files

clk: samsung: Use cached clk_hws instead of __clk_lookup() calls 



For the CPU clock registration two parent clocks are required, these
are now being passed as struct clk_hw pointers, rather than by the
global scope names. That allows us to avoid  __clk_lookup() calls
and simplifies a bit the CPU clock registration function.
While at it drop unneeded extern keyword in the function declaration.

Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com


Reported-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 1f6e17d2

drivers/clk/samsung/clk-cpu.c

+15 −22
Original line number Diff line number Diff line
@@ -401,26 +401,34 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb, 


/* helper function to register a CPU clock */

int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,

		unsigned int lookup_id, const char *name, const char *parent,

		const char *alt_parent, unsigned long offset,

		const struct exynos_cpuclk_cfg_data *cfg,

		unsigned int lookup_id, const char *name,

		const struct clk_hw *parent, const struct clk_hw *alt_parent,

		unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,

		unsigned long num_cfgs, unsigned long flags)

{

	struct exynos_cpuclk *cpuclk;

	struct clk_init_data init;

	struct clk *parent_clk;

	const char *parent_name;

	int ret = 0;



	if (IS_ERR(parent) || IS_ERR(alt_parent)) {

		pr_err("%s: invalid parent clock(s)\n", __func__);

		return -EINVAL;

	}



	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);

	if (!cpuclk)

		return -ENOMEM;



	parent_name = clk_hw_get_name(parent);



	init.name = name;

	init.flags = CLK_SET_RATE_PARENT;

	init.parent_names = &parent;

	init.parent_names = &parent_name;

	init.num_parents = 1;

	init.ops = &exynos_cpuclk_clk_ops;



	cpuclk->alt_parent = alt_parent;

	cpuclk->hw.init = &init;

	cpuclk->ctrl_base = ctx->reg_base + offset;

	cpuclk->lock = &ctx->lock;
@@ -430,23 +438,8 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 
	else

		cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;



	cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));

	if (!cpuclk->alt_parent) {

		pr_err("%s: could not lookup alternate parent %s\n",

				__func__, alt_parent);

		ret = -EINVAL;

		goto free_cpuclk;

	}



	parent_clk = __clk_lookup(parent);

	if (!parent_clk) {

		pr_err("%s: could not lookup parent clock %s\n",

				__func__, parent);

		ret = -EINVAL;

		goto free_cpuclk;

	}



	ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);

	ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);

	if (ret) {

		pr_err("%s: failed to register clock notifier for %s\n",

				__func__, name);
@@ -471,7 +464,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 
free_cpuclk_data:

	kfree(cpuclk->cfg);

unregister_clk_nb:

	clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);

	clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);

free_cpuclk:

	kfree(cpuclk);

	return ret;

drivers/clk/samsung/clk-cpu.h

+3 −3
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ struct exynos_cpuclk_cfg_data { 
 */

struct exynos_cpuclk {

	struct clk_hw				hw;

	struct clk_hw				*alt_parent;

	const struct clk_hw			*alt_parent;

	void __iomem				*ctrl_base;

	spinlock_t				*lock;

	const struct exynos_cpuclk_cfg_data	*cfg;
@@ -62,9 +62,9 @@ struct exynos_cpuclk { 
#define CLK_CPU_HAS_E5433_REGS_LAYOUT	(1 << 2)

};



extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,

int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,

			unsigned int lookup_id, const char *name,

			const char *parent, const char *alt_parent,

			const struct clk_hw *parent, const struct clk_hw *alt_parent,

			unsigned long offset,

			const struct exynos_cpuclk_cfg_data *cfg,

			unsigned long num_cfgs, unsigned long flags);

drivers/clk/samsung/clk-exynos3250.c

+4 −2
Original line number Diff line number Diff line
@@ -808,14 +808,16 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { 
static void __init exynos3250_cmu_init(struct device_node *np)

{

	struct samsung_clk_provider *ctx;

	struct clk_hw **hws;



	ctx = samsung_cmu_register_one(np, &cmu_info);

	if (!ctx)

		return;



	hws = ctx->clk_data.hws;

	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_core_p[0], mout_core_p[1], 0x14200,

			e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),

			hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],

			0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),

			CLK_CPU_HAS_DIV1);



	exynos3_core_down_clock(ctx->reg_base);

drivers/clk/samsung/clk-exynos4.c

+5 −2
Original line number Diff line number Diff line
@@ -1233,6 +1233,8 @@ static void __init exynos4_clk_init(struct device_node *np, 
				    enum exynos4_soc soc)

{

	struct samsung_clk_provider *ctx;

	struct clk_hw **hws;



	exynos4_soc = soc;



	reg_base = of_iomap(np, 0);
@@ -1240,6 +1242,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
		panic("%s: failed to map registers\n", __func__);



	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	hws = ctx->clk_data.hws;



	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
@@ -1302,7 +1305,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
			exynos4210_fixed_factor_clks,

			ARRAY_SIZE(exynos4210_fixed_factor_clks));

		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_core_p4210[0], mout_core_p4210[1], 0x14200,

			hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,

			e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),

			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);

	} else {
@@ -1317,7 +1320,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
			ARRAY_SIZE(exynos4x12_fixed_factor_clks));



		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,

			hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,

			e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),

			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);

	}

drivers/clk/samsung/clk-exynos5250.c

+3 −1
Original line number Diff line number Diff line
@@ -782,6 +782,7 @@ static void __init exynos5250_clk_init(struct device_node *np) 
{

	struct samsung_clk_provider *ctx;

	unsigned int tmp;

	struct clk_hw **hws;



	if (np) {

		reg_base = of_iomap(np, 0);
@@ -792,6 +793,7 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	}



	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	hws = ctx->clk_data.hws;



	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
@@ -821,7 +823,7 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	samsung_clk_register_gate(ctx, exynos5250_gate_clks,

			ARRAY_SIZE(exynos5250_gate_clks));

	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_cpu_p[0], mout_cpu_p[1], 0x200,

			hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,

			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),

			CLK_CPU_HAS_DIV1);

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