ARC: [plat-axs10x] DTS: Add reset controller node to manage ethernet reset (ff64d695) · Commits · 戴 / test

DW ethernet controller on axs10x hangs sometimes after SW reset. Invoke the newly aded driver (reset-axs10x.c) by adding the DT bits. With this in place, we don't need the open-coded quirk in platform code, so get rid of it as well ! Signed-off-by:

Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by:

Vineet Gupta <vgupta@synopsys.com> Signed-off-by:

Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by:

Vineet Gupta <vgupta@synopsys.com>

arch/arc/boot/dts/axs10x_mb.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -16,6 +16,12 @@
		ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
		interrupt-parent = <&mb_intc>;

		creg_rst: reset-controller@11220 {
		compatible = "snps,axs10x-reset";
		#reset-cells = <1>;
		reg = <0x11220 0x4>;
		};

		i2sclk: i2sclk@100a0 {
		compatible = "snps,axs10x-i2s-pll-clock";
		reg = <0x100a0 0x10>;
		@@ -73,6 +79,8 @@
		clocks = <&apbclk>;
		clock-names = "stmmaceth";
		max-speed = <100>;
		resets = <&creg_rst 5>;
		reset-names = "stmmaceth";
		};

		ehci@0x40000 {

arch/arc/plat-axs10x/axs10x.c

+0 −7

Original line number	Diff line number	Diff line
		@@ -111,13 +111,6 @@ static void __init axs10x_early_init(void)

		axs10x_enable_gpio_intc_wire();

		/*
		* Reset ethernet IP core.
		* TODO: get rid of this quirk after axs10x reset driver (or simple
		* reset driver) will be available in upstream.
		*/
		iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);

		scnprintf(mb, 32, "MainBoard v%d", mb_rev);
		axs10x_print_board_ver(CREG_MB_VER, mb);
		}

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