Commit feec1277 authored by Paul Walmsley's avatar Paul Walmsley
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OMAP2/3/4 clock: omap2_clk_prepare_for_reboot() is OMAP2xxx-only 



omap2_clk_prepare_for_reboot() is only applicable to OMAP2xxx chips,
so rename it to omap2xxx_clk_prepare_for_reboot() and only call it when
running on OMAP2xxx chips.  Remove the old stub in the OMAP3 clock code.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent da4d2904

arch/arm/mach-omap2/clock.h

+0 −1
Original line number Diff line number Diff line
@@ -84,7 +84,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); 
u32 omap2_get_dpll_rate(struct clk *clk);

void omap2_init_dpll_parent(struct clk *clk);

int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);

void omap2_clk_prepare_for_reboot(void);

int omap2_dflt_clk_enable(struct clk *clk);

void omap2_dflt_clk_disable(struct clk *clk);

void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,

arch/arm/mach-omap2/clock2xxx.c

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ const struct clkops clkops_omap2430_i2chs_wait = { 
/*

 * Set clocks for bypass mode for reboot to work.

 */

void omap2_clk_prepare_for_reboot(void)

void omap2xxx_clk_prepare_for_reboot(void)

{

	u32 rate;

arch/arm/mach-omap2/clock2xxx.h

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);

u32 omap2xxx_get_apll_clkin(void);

u32 omap2xxx_get_sysclkdiv(void);

void omap2xxx_clk_prepare_for_reboot(void);



/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */

#ifdef CONFIG_ARCH_OMAP2420

arch/arm/mach-omap2/clock34xx.c

+2 −19
Original line number Diff line number Diff line
@@ -150,25 +150,6 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) 
	return omap3_noncore_dpll_set_rate(clk, rate);

}



/* Common clock code */



/*

 * Set clocks for bypass mode for reboot to work.

 */

void omap2_clk_prepare_for_reboot(void)

{

	/* REVISIT: Not ready for 343x */

#if 0

	u32 rate;



	if (vclk == NULL || sclk == NULL)

		return;



	rate = clk_get_rate(sclk);

	clk_set_rate(vclk, rate);

#endif

}



void omap3_clk_lock_dpll5(void)

{

	struct clk *dpll5_clk;
@@ -191,6 +172,8 @@ void omap3_clk_lock_dpll5(void) 
	return;

}



/* Common clock code */



/* REVISIT: Move this init stuff out into clock.c */



/*

arch/arm/mach-omap2/clock44xx.c

+0 −5
Original line number Diff line number Diff line
@@ -17,8 +17,3 @@ const struct clkops clkops_noncore_dpll_ops = { 
	.enable		= &omap3_noncore_dpll_enable,

	.disable	= &omap3_noncore_dpll_disable,

};
 


void omap2_clk_prepare_for_reboot(void)

{

	return;

}

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