Commit fec9434a authored by David Woodhouse's avatar David Woodhouse Committed by Thomas Gleixner
Browse files

x86/pti: Do not enable PTI on CPUs which are not vulnerable to Meltdown 



Also, for CPUs which don't speculate at all, don't report that they're
vulnerable to the Spectre variants either.

Leave the cpu_no_meltdown[] match table with just X86_VENDOR_AMD in it
for now, even though that could be done with a simple comparison, on the
assumption that we'll have more to add.

Based on suggestions from Dave Hansen and Alan Cox.

Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Acked-by: default avatarDave Hansen <dave.hansen@intel.com>
Cc: gnomes@lxorguk.ukuu.org.uk
Cc: ak@linux.intel.com
Cc: ashok.raj@intel.com
Cc: karahmed@amazon.de
Cc: arjan@linux.intel.com
Cc: torvalds@linux-foundation.org
Cc: peterz@infradead.org
Cc: bp@alien8.de
Cc: pbonzini@redhat.com
Cc: tim.c.chen@linux.intel.com
Cc: gregkh@linux-foundation.org
Link: https://lkml.kernel.org/r/1516896855-7642-6-git-send-email-dwmw@amazon.co.uk
parent 1e340c60

arch/x86/kernel/cpu/common.c

+43 −5
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ 
#include <asm/pat.h>

#include <asm/microcode.h>

#include <asm/microcode_intel.h>

#include <asm/intel-family.h>

#include <asm/cpu_device_id.h>



#ifdef CONFIG_X86_LOCAL_APIC

#include <asm/uv/uv.h>
@@ -853,6 +855,41 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) 
#endif

}



static const __initdata struct x86_cpu_id cpu_no_speculation[] = {

	{ X86_VENDOR_INTEL,	6, INTEL_FAM6_ATOM_CEDARVIEW,	X86_FEATURE_ANY },

	{ X86_VENDOR_INTEL,	6, INTEL_FAM6_ATOM_CLOVERVIEW,	X86_FEATURE_ANY },

	{ X86_VENDOR_INTEL,	6, INTEL_FAM6_ATOM_LINCROFT,	X86_FEATURE_ANY },

	{ X86_VENDOR_INTEL,	6, INTEL_FAM6_ATOM_PENWELL,	X86_FEATURE_ANY },

	{ X86_VENDOR_INTEL,	6, INTEL_FAM6_ATOM_PINEVIEW,	X86_FEATURE_ANY },

	{ X86_VENDOR_CENTAUR,	5 },

	{ X86_VENDOR_INTEL,	5 },

	{ X86_VENDOR_NSC,	5 },

	{ X86_VENDOR_ANY,	4 },

	{}

};



static const __initdata struct x86_cpu_id cpu_no_meltdown[] = {

	{ X86_VENDOR_AMD },

	{}

};



static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c)

{

	u64 ia32_cap = 0;



	if (x86_match_cpu(cpu_no_meltdown))

		return false;



	if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))

		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);



	/* Rogue Data Cache Load? No! */

	if (ia32_cap & ARCH_CAP_RDCL_NO)

		return false;



	return true;

}



/*

 * Do minimum CPU detection early.

 * Fields really needed: vendor, cpuid_level, family, model, mask,
@@ -900,11 +937,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) 


	setup_force_cpu_cap(X86_FEATURE_ALWAYS);



	if (c->x86_vendor != X86_VENDOR_AMD)

	if (!x86_match_cpu(cpu_no_speculation)) {

		if (cpu_vulnerable_to_meltdown(c))

			setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);



		setup_force_cpu_bug(X86_BUG_SPECTRE_V1);

		setup_force_cpu_bug(X86_BUG_SPECTRE_V2);

	}



	fpu__init_system(c);

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