Unverified Commit fe7cd97e authored by Paul Burton's avatar Paul Burton
Browse files

MIPS: bitops: Handle !kernel_uses_llsc first 



Reorder conditions in our various bitops functions that check
kernel_uses_llsc such that they handle the !kernel_uses_llsc case first.
This allows us to avoid the need to duplicate the kernel_uses_llsc check
in all the other cases. For functions that don't involve barriers common
to the various implementations, we switch to returning from within each
if block making each case easier to read in isolation.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
parent 1da7bce8

arch/mips/include/asm/bitops.h

+105 −108
Original line number Diff line number Diff line
@@ -56,7 +56,12 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
	int bit = nr & SZLONG_MASK;

	unsigned long temp;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	if (!kernel_uses_llsc) {

		__mips_set_bit(nr, addr);

		return;

	}



	if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -68,8 +73,11 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
		: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m)

		: __LLSC_CLOBBER);

		return;

	}



#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {

	if (__builtin_constant_p(bit)) {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -80,8 +88,10 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
			: "ir" (bit), "r" (~0)

			: __LLSC_CLOBBER);

		} while (unlikely(!temp));

		return;

	}

#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */

	} else if (kernel_uses_llsc) {



	loongson_llsc_mb();

	do {

		__asm__ __volatile__(
@@ -95,8 +105,6 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
		: "ir" (1UL << bit)

		: __LLSC_CLOBBER);

	} while (unlikely(!temp));

	} else

		__mips_set_bit(nr, addr);

}



/*
@@ -115,7 +123,12 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
	int bit = nr & SZLONG_MASK;

	unsigned long temp;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	if (!kernel_uses_llsc) {

		__mips_clear_bit(nr, addr);

		return;

	}



	if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -127,8 +140,11 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (~(1UL << bit))

		: __LLSC_CLOBBER);

		return;

	}



#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {

	if (__builtin_constant_p(bit)) {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -139,8 +155,10 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
			: "ir" (bit)

			: __LLSC_CLOBBER);

		} while (unlikely(!temp));

		return;

	}

#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */

	} else if (kernel_uses_llsc) {



	loongson_llsc_mb();

	do {

		__asm__ __volatile__(
@@ -154,8 +172,6 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
		: "ir" (~(1UL << bit))

		: __LLSC_CLOBBER);

	} while (unlikely(!temp));

	} else

		__mips_clear_bit(nr, addr);

}



/*
@@ -183,12 +199,16 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad 
 */

static inline void change_bit(unsigned long nr, volatile unsigned long *addr)

{

	int bit = nr & SZLONG_MASK;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);

	int bit = nr & SZLONG_MASK;

	unsigned long temp;



	if (!kernel_uses_llsc) {

		__mips_change_bit(nr, addr);

		return;

	}



	if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push				\n"

		"	.set	arch=r4000			\n"
@@ -200,9 +220,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (1UL << bit)

		: __LLSC_CLOBBER);

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;

		return;

	}



	loongson_llsc_mb();

	do {
@@ -217,8 +236,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
		: "ir" (1UL << bit)

		: __LLSC_CLOBBER);

	} while (unlikely(!temp));

	} else

		__mips_change_bit(nr, addr);

}



/*
@@ -232,15 +249,15 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
static inline int test_and_set_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);

	int bit = nr & SZLONG_MASK;

	unsigned long res;

	unsigned long res, temp;



	smp_mb__before_llsc();



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	if (!kernel_uses_llsc) {

		res = __mips_test_and_set_bit(nr, addr);

	} else if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -253,10 +270,7 @@ static inline int test_and_set_bit(unsigned long nr, 
		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

		: "r" (1UL << bit)

		: __LLSC_CLOBBER);

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	} else {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -272,8 +286,7 @@ static inline int test_and_set_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else

		res = __mips_test_and_set_bit(nr, addr);

	}



	smp_llsc_mb();
@@ -291,13 +304,13 @@ static inline int test_and_set_bit(unsigned long nr, 
static inline int test_and_set_bit_lock(unsigned long nr,

	volatile unsigned long *addr)

{

	int bit = nr & SZLONG_MASK;

	unsigned long res;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

	unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);

		unsigned long temp;

	int bit = nr & SZLONG_MASK;

	unsigned long res, temp;



	if (!kernel_uses_llsc) {

		res = __mips_test_and_set_bit_lock(nr, addr);

	} else if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -310,11 +323,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
		: "=&r" (temp), "+m" (*m), "=&r" (res)

		: "r" (1UL << bit)

		: __LLSC_CLOBBER);

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



		loongson_llsc_mb();

	} else {

		do {

			__asm__ __volatile__(

			"	.set	push				\n"
@@ -329,8 +338,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else

		res = __mips_test_and_set_bit_lock(nr, addr);

	}



	smp_llsc_mb();
@@ -347,15 +355,15 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
static inline int test_and_clear_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);

	int bit = nr & SZLONG_MASK;

	unsigned long res;

	unsigned long res, temp;



	smp_mb__before_llsc();



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	if (!kernel_uses_llsc) {

		res = __mips_test_and_clear_bit(nr, addr);

	} else if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -370,10 +378,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
		: "r" (1UL << bit)

		: __LLSC_CLOBBER);

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)

	} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	} else if (__builtin_constant_p(nr)) {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -386,10 +391,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
			: __LLSC_CLOBBER);

		} while (unlikely(!temp));

#endif

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	} else {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -406,8 +408,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else

		res = __mips_test_and_clear_bit(nr, addr);

	}



	smp_llsc_mb();
@@ -425,15 +426,15 @@ static inline int test_and_clear_bit(unsigned long nr, 
static inline int test_and_change_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned long *m = ((unsigned long *)addr) + (nr >> SZLONG_LOG);

	int bit = nr & SZLONG_MASK;

	unsigned long res;

	unsigned long res, temp;



	smp_mb__before_llsc();



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	if (!kernel_uses_llsc) {

		res = __mips_test_and_change_bit(nr, addr);

	} else if (R10000_LLSC_WAR) {

		__asm__ __volatile__(

		"	.set	push					\n"

		"	.set	arch=r4000				\n"
@@ -446,10 +447,7 @@ static inline int test_and_change_bit(unsigned long nr, 
		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

		: "r" (1UL << bit)

		: __LLSC_CLOBBER);

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

		unsigned long temp;



	} else {

		loongson_llsc_mb();

		do {

			__asm__ __volatile__(
@@ -465,8 +463,7 @@ static inline int test_and_change_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else

		res = __mips_test_and_change_bit(nr, addr);

	}



	smp_llsc_mb();

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