Commit fe7c20fa authored by Ulrich Hecht's avatar Ulrich Hecht Committed by Simon Horman
Browse files

ARM: shmobile: r8a7740 dtsi: add remaining DIV6 clocks 



This adds the remaining DIV6 clocks and all possible parents for the SUB
clock.

Signed-off-by: default avatarUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c517d838

arch/arm/boot/dts/r8a7740.dtsi

+78 −1
Original line number Diff line number Diff line
@@ -431,6 +431,18 @@ 
			clock-frequency = <27000000>;

			clock-output-names = "dv";

		};

		fmsick_clk: fmsick_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "fmsick";

		};

		fmsock_clk: fmsock_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <0>;

			clock-output-names = "fmsock";

		};

		fsiack_clk: fsiack_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;
@@ -459,13 +471,78 @@ 
		};



		/* Variable factor clocks (DIV6) */

		vclk1_clk: vclk1_clk@e6150008 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150008 4>;

			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>,

				 <&extal1_div2_clk>, <&extalr_clk>, <0>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk1";

		};

		vclk2_clk: vclk2_clk@e615000c {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe615000c 4>;

			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>,

				 <&extal1_div2_clk>, <&extalr_clk>, <0>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk2";

		};

		fmsi_clk: fmsi_clk@e6150010 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150010 4>;

			clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fmsi";

		};

		fmso_clk: fmso_clk@e6150014 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150014 4>;

			clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fmso";

		};

		fsia_clk: fsia_clk@e6150018 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150018 4>;

			clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fsia";

		};

		sub_clk: sub_clk@e6150080 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150080 4>;

			clocks = <&pllc1_div2_clk>;

			clocks = <&pllc1_div2_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "sub";

		};

		spu_clk: spu_clk@e6150084 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150084 4>;

			clocks = <&pllc1_div2_clk>,

				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "spu";

		};

		vou_clk: vou_clk@e6150088 {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe6150088 4>;

			clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,

				 <0>;

			#clock-cells = <0>;

			clock-output-names = "vou";

		};

		stpro_clk: stpro_clk@e615009c {

			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";

			reg = <0xe615009c 4>;

			clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;

			#clock-cells = <0>;

			clock-output-names = "stpro";

		};



		/* Fixed factor clocks */

		pllc1_div2_clk: pllc1_div2_clk {

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