Commit fe671772 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/85xx: Use fsl,mpc85.. as prefix for memory ctrl & l2-cache nodes 



Older devices tree's used "fsl,85.." instead of the preferred
"fsl,mpc85.." for the memory controller & l2 cache controller nodes.
The EDAC code is the only use of these and has been updated for some
time to support both "fsl,85.." and "fsl,mpc85.."

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9310933c

arch/powerpc/boot/dts/ksi8560.dts

+2 −2
Original line number Diff line number Diff line
@@ -57,14 +57,14 @@ 
		bus-frequency = <0>;				/* Fixed by bootwrapper */



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			compatible = "fsl,mpc8540-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <0x12 0x2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			compatible = "fsl,mpc8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <0x20>;		/* 32 bytes */

			cache-size = <0x40000>;			/* L2, 256K */

arch/powerpc/boot/dts/sbc8548.dts

+2 −2
Original line number Diff line number Diff line
@@ -156,14 +156,14 @@ 
		compatible = "simple-bus";



		memory-controller@2000 {

			compatible = "fsl,8548-memory-controller";

			compatible = "fsl,mpc8548-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <0x12 0x2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8548-l2-cache-controller";

			compatible = "fsl,mpc8548-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <0x20>;	// 32 bytes

			cache-size = <0x80000>;	// L2, 512K

arch/powerpc/boot/dts/sbc8560.dts

+2 −2
Original line number Diff line number Diff line
@@ -61,14 +61,14 @@ 
		clock-frequency = <0>;



		memory-controller@2000 {

			compatible = "fsl,8560-memory-controller";

			compatible = "fsl,mpc8560-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <0x12 0x2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8560-l2-cache-controller";

			compatible = "fsl,mpc8560-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <0x20>;	// 32 bytes

			cache-size = <0x40000>;		// L2, 256K

arch/powerpc/boot/dts/stx_gp3_8560.dts

+2 −2
Original line number Diff line number Diff line
@@ -57,14 +57,14 @@ 
		compatible = "fsl,mpc8560-immr", "simple-bus";



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			compatible = "fsl,mpc8540-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			compatible = "fsl,mpc8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;

			cache-size = <0x40000>;	// L2, 256K

arch/powerpc/boot/dts/tqm8540.dts

+2 −2
Original line number Diff line number Diff line
@@ -59,14 +59,14 @@ 
		compatible = "fsl,mpc8540-immr", "simple-bus";



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			compatible = "fsl,mpc8540-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			compatible = "fsl,mpc8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;

			cache-size = <0x40000>;	// L2, 256K

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