Commit fe621fde authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "A Samsung driver fix and a handful of TI driver fixes"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: ti: dflt: fix enable_reg validity check
  clk: ti: fix dual-registration of uart4_ick
  clk: ti: clk-7xx: Remove hardwired ABE clock configuration
  clk: samsung: fix cpu clock's flags checking
parents 8140e736 9f30a04d

drivers/clk/samsung/clk-cpu.c

+5 −5
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, 
	 * the values for DIV_COPY and DIV_HPM dividers need not be set.

	 */

	div0 = cfg_data->div0;

	if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {

	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {

		div1 = cfg_data->div1;

		if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)

			div1 = readl(base + E4210_DIV_CPU1) &
@@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, 
		alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;

		WARN_ON(alt_div >= MAX_DIV);



		if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {

		if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {

			/*

			 * In Exynos4210, ATB clock parent is also mout_core. So

			 * ATB clock also needs to be mantained at safe speed.
@@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, 
	writel(div0, base + E4210_DIV_CPU0);

	wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);



	if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) {

	if (cpuclk->flags & CLK_CPU_HAS_DIV1) {

		writel(div1, base + E4210_DIV_CPU1);

		wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,

				DIV_MASK_ALL);
@@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, 
	unsigned long mux_reg;



	/* find out the divider values to use for clock data */

	if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {

	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {

		while ((cfg_data->prate * 1000) != ndata->new_rate) {

			if (cfg_data->prate == 0)

				return -EINVAL;
@@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, 
	writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);

	wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);



	if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) {

	if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {

		div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);

		div_mask |= E4210_DIV0_ATB_MASK;

	}

drivers/clk/ti/clk-3xxx.c

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,6 @@ static struct ti_dt_clk omap3xxx_clks[] = { 
	DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),

	DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),

	DT_CLK(NULL, "uart3_ick", "uart3_ick"),

	DT_CLK(NULL, "uart4_ick", "uart4_ick"),

	DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),

	DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),

	DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
@@ -519,6 +518,7 @@ static struct ti_dt_clk am35xx_clks[] = { 
static struct ti_dt_clk omap36xx_clks[] = {

	DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),

	DT_CLK(NULL, "uart4_fck", "uart4_fck"),

	DT_CLK(NULL, "uart4_ick", "uart4_ick"),

	{ .node_name = NULL },

};

drivers/clk/ti/clk-7xx.c

+1 −17
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 


#include "clock.h"



#define DRA7_DPLL_ABE_DEFFREQ				180633600

#define DRA7_DPLL_GMAC_DEFFREQ				1000000000

#define DRA7_DPLL_USB_DEFFREQ				960000000
@@ -313,27 +312,12 @@ static struct ti_dt_clk dra7xx_clks[] = { 
int __init dra7xx_dt_clk_init(void)

{

	int rc;

	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck;

	struct clk *dpll_ck, *hdcp_ck;



	ti_dt_clocks_register(dra7xx_clks);



	omap2_clk_disable_autoidle_all();



	abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux");

	sys_clkin2 = clk_get_sys(NULL, "sys_clkin2");

	dpll_ck = clk_get_sys(NULL, "dpll_abe_ck");



	rc = clk_set_parent(abe_dpll_mux, sys_clkin2);

	if (!rc)

		rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ);

	if (rc)

		pr_err("%s: failed to configure ABE DPLL!\n", __func__);



	dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");

	rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);

	if (rc)

		pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);



	dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");

	rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);

	if (rc)

drivers/clk/ti/clkt_dflt.c

+2 −2
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ int omap2_dflt_clk_enable(struct clk_hw *hw) 
		}

	}



	if (unlikely(!clk->enable_reg)) {

	if (unlikely(IS_ERR(clk->enable_reg))) {

		pr_err("%s: %s missing enable_reg\n", __func__,

		       clk_hw_get_name(hw));

		ret = -EINVAL;
@@ -264,7 +264,7 @@ void omap2_dflt_clk_disable(struct clk_hw *hw) 
	u32 v;



	clk = to_clk_hw_omap(hw);

	if (!clk->enable_reg) {

	if (IS_ERR(clk->enable_reg)) {

		/*

		 * 'independent' here refers to a clock which is not

		 * controlled by its parent.

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