Commit fe5211f1 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: add reset_ras_error_count function for MMHUB 



MMHUB ras error counters are dirty ones after cold reboot
Read operation is needed to reset them to 0

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86153f1b

drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ struct amdgpu_mmhub_funcs { 
	int (*ras_late_init)(struct amdgpu_device *adev);

	void (*query_ras_error_count)(struct amdgpu_device *adev,

					void *ras_error_status);

	void (*reset_ras_error_count)(struct amdgpu_device *adev);

};



struct amdgpu_mmhub {

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -948,6 +948,9 @@ static int gmc_v9_0_late_init(void *handle) 
		}

	}



	if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)

		adev->mmhub.funcs->reset_ras_error_count(adev);



	r = amdgpu_gmc_ras_late_init(adev);

	if (r)

		return r;

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+12 −0
Original line number Diff line number Diff line
@@ -747,7 +747,19 @@ static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev, 
	err_data->ue_count += ded_count;

}



static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev)

{

	uint32_t i;



	/* read back edc counter registers to reset the counters to 0 */

	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {

		for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++)

			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));

	}

}



const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {

	.ras_late_init = amdgpu_mmhub_ras_late_init,

	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,

	.reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,

};

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

+12 −0
Original line number Diff line number Diff line
@@ -1596,7 +1596,19 @@ static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev, 
	err_data->ue_count += ded_count;

}



static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)

{

	uint32_t i;



	/* read back edc counter registers to reset the counters to 0 */

	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {

		for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)

			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));

	}

}



const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {

	.ras_late_init = amdgpu_mmhub_ras_late_init,

	.query_ras_error_count = mmhub_v9_4_query_ras_error_count,

	.reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,

};

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