Commit fe34464d authored by Stephane Viau's avatar Stephane Viau Committed by Rob Clark
Browse files

drm/msm/mdp5: Fix iteration on INTF config array 



The current iteration in get_dsi_id_from_intf() is wrong:
instead of iterating until hw_cfg->intf.count, we need to iterate
until MDP5_INTF_NUM_MAX here.

Let's take the example of msm8x16:

 hw_cfg->intf.count = 1
 intfs[0] = INTF_Disabled
 intfs[1] = INTF_DSI

If we stop iterating once i reaches hw_cfg->intf.count (== 1),
we will miss the test for intfs[1].

Actually, this hw_cfg->intf.count entry is quite confusing and is not
(or *should not be*) used anywhere else; let's remove it.

Signed-off-by: default avatarStephane Viau <sviau@codeaurora.org>
parent 651ad3f5

drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c

+17 −17
Original line number Diff line number Diff line
@@ -72,15 +72,14 @@ const struct mdp5_cfg_hw msm8x74_config = { 
		.base = { 0x12d00, 0x12e00, 0x12f00 },

	},

	.intf = {

		.count = 4,

		.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },

	},

	.intfs = {

		.connect = {

			[0] = INTF_eDP,

			[1] = INTF_DSI,

			[2] = INTF_DSI,

			[3] = INTF_HDMI,

		},

	},

	.max_clk = 200000000,

};
@@ -142,15 +141,14 @@ const struct mdp5_cfg_hw apq8084_config = { 
		.base = { 0x12f00, 0x13000, 0x13100, 0x13200 },

	},

	.intf = {

		.count = 5,

		.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },

	},

	.intfs = {

		.connect = {

			[0] = INTF_eDP,

			[1] = INTF_DSI,

			[2] = INTF_DSI,

			[3] = INTF_HDMI,

		},

	},

	.max_clk = 320000000,

};
@@ -196,10 +194,12 @@ const struct mdp5_cfg_hw msm8x16_config = { 


	},

	.intf = {

		.count = 1, /* INTF_1 */

		.base = { 0x6B800 },

		.base = { 0x00000, 0x6b800 },

		.connect = {

			[0] = INTF_DISABLED,

			[1] = INTF_DSI,

		},

	},

	/* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */

	.max_clk = 320000000,

};

drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h

+6 −3
Original line number Diff line number Diff line
@@ -59,6 +59,11 @@ struct mdp5_smp_block { 


#define MDP5_INTF_NUM_MAX	5



struct mdp5_intf_block {

	uint32_t base[MAX_BASES];

	u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */

};



struct mdp5_cfg_hw {

	char  *name;
@@ -72,9 +77,7 @@ struct mdp5_cfg_hw { 
	struct mdp5_sub_block dspp;

	struct mdp5_sub_block ad;

	struct mdp5_sub_block pp;

	struct mdp5_sub_block intf;



	u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */

	struct mdp5_intf_block intf;



	uint32_t max_clk;

};

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c

+6 −6
Original line number Diff line number Diff line
@@ -206,8 +206,8 @@ static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 


static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)

{

	const int intf_cnt = hw_cfg->intf.count;

	const u32 *intfs = hw_cfg->intfs;

	const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;

	const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);

	int id = 0, i;



	for (i = 0; i < intf_cnt; i++) {
@@ -228,7 +228,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) 
	struct msm_drm_private *priv = dev->dev_private;

	const struct mdp5_cfg_hw *hw_cfg =

					mdp5_cfg_get_hw_config(mdp5_kms->cfg);

	enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num];

	enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];

	struct drm_encoder *encoder;

	int ret = 0;
@@ -365,7 +365,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) 
	/* Construct encoders and modeset initialize connector devices

	 * for each external display interface.

	 */

	for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) {

	for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {

		ret = modeset_init_intf(mdp5_kms, i);

		if (ret)

			goto fail;
@@ -514,8 +514,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 
	 */

	mdp5_enable(mdp5_kms);

	for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {

		if (!config->hw->intf.base[i] ||

				mdp5_cfg_intf_is_virtual(config->hw->intfs[i]))

		if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||

				!config->hw->intf.base[i])

			continue;

		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);

	}

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