Commit fe12e943 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'gpio-v5.5-updates-for-linus-part-1' of... 

Merge tag 'gpio-v5.5-updates-for-linus-part-1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel

gpio updates for v5.5

- only get the second IRQ when there is more than one IRQ in mxc
- move the code around in lineevent_create() for some shrinkage
- fix formatting for GPIO docs
- add DT binding for r8a774b1
- convert drivers that prevously used nocache ioremap() to using regular
  devm_platform_ioremap_resource()
- remove some redundant error messages
- shrink object code in 104-idi-48e
- drop an unneeded warning from gpiolib-of
parents 698b8eea 228fc010

Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 
    - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.

    - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller.

    - "renesas,gpio-r8a774a1": for R8A774A1 (RZ/G2M) compatible GPIO controller.

    - "renesas,gpio-r8a774b1": for R8A774B1 (RZ/G2N) compatible GPIO controller.

    - "renesas,gpio-r8a774c0": for R8A774C0 (RZ/G2E) compatible GPIO controller.

    - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.

    - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.

Documentation/driver-api/gpio/driver.rst

+4 −0
Original line number Diff line number Diff line
@@ -415,6 +415,8 @@ If you do this, the additional irq_chip will be set up by gpiolib at the 
same time as setting up the rest of the GPIO functionality. The following

is a typical example of a cascaded interrupt handler using gpio_irq_chip:



.. code-block:: c



  /* Typical state container with dynamic irqchip */

  struct my_gpio {

      struct gpio_chip gc;
@@ -450,6 +452,8 @@ is a typical example of a cascaded interrupt handler using gpio_irq_chip: 
The helper support using hierarchical interrupt controllers as well.

In this case the typical set-up will look like this:



.. code-block:: c



  /* Typical state container with dynamic irqchip */

  struct my_gpio {

      struct gpio_chip gc;

drivers/gpio/gpio-104-idi-48.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset) 
{

	struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);

	unsigned i;

	const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };

	static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 };

	unsigned base_offset;

	unsigned mask;

drivers/gpio/gpio-ath79.c

+3 −7
Original line number Diff line number Diff line
@@ -226,7 +226,6 @@ static int ath79_gpio_probe(struct platform_device *pdev) 
	struct device_node *np = dev->of_node;

	struct ath79_gpio_ctrl *ctrl;

	struct gpio_irq_chip *girq;

	struct resource *res;

	u32 ath79_gpio_count;

	bool oe_inverted;

	int err;
@@ -256,12 +255,9 @@ static int ath79_gpio_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res)

		return -EINVAL;

	ctrl->base = devm_ioremap_nocache(dev, res->start, resource_size(res));

	if (!ctrl->base)

		return -ENOMEM;

	ctrl->base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(ctrl->base))

		return PTR_ERR(ctrl->base);



	raw_spin_lock_init(&ctrl->lock);

	err = bgpio_init(&ctrl->gc, dev, 4,

drivers/gpio/gpio-em.c

+8 −12
Original line number Diff line number Diff line
@@ -269,7 +269,7 @@ static void em_gio_irq_domain_remove(void *data) 
static int em_gio_probe(struct platform_device *pdev)

{

	struct em_gio_priv *p;

	struct resource *io[2], *irq[2];

	struct resource *irq[2];

	struct gpio_chip *gpio_chip;

	struct irq_chip *irq_chip;

	struct device *dev = &pdev->dev;
@@ -285,25 +285,21 @@ static int em_gio_probe(struct platform_device *pdev) 
	platform_set_drvdata(pdev, p);

	spin_lock_init(&p->sense_lock);



	io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);

	irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);

	irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);



	if (!io[0] || !io[1] || !irq[0] || !irq[1]) {

	if (!irq[0] || !irq[1]) {

		dev_err(dev, "missing IRQ or IOMEM\n");

		return -EINVAL;

	}



	p->base0 = devm_ioremap_nocache(dev, io[0]->start,

					resource_size(io[0]));

	if (!p->base0)

		return -ENOMEM;

	p->base0 = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(p->base0))

		return PTR_ERR(p->base0);



	p->base1 = devm_ioremap_nocache(dev, io[1]->start,

				   resource_size(io[1]));

	if (!p->base1)

		return -ENOMEM;

	p->base1 = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(p->base1))

		return PTR_ERR(p->base1);



	if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {

		dev_err(dev, "Missing ngpios OF property\n");

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