Commit fdd5faaa authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: cleanup vm_size handling 



It's pointless to have the same value twice, just always use max_pfn.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c47b41a7

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+9 −9
Original line number Diff line number Diff line
@@ -2576,26 +2576,26 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, 
 * @adev: amdgpu_device pointer

 * @vm_size: the default vm size if it's set auto

 */

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

			   uint32_t fragment_size_default)

{

	/* adjust vm size firstly */

	if (amdgpu_vm_size == -1)

		adev->vm_manager.vm_size = vm_size;

	else

		adev->vm_manager.vm_size = amdgpu_vm_size;

	if (amdgpu_vm_size != -1)

		vm_size = amdgpu_vm_size;



	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;



	/* block size depends on vm size */

	if (amdgpu_vm_block_size == -1)

		adev->vm_manager.block_size =

			amdgpu_vm_get_block_size(adev->vm_manager.vm_size);

			amdgpu_vm_get_block_size(vm_size);

	else

		adev->vm_manager.block_size = amdgpu_vm_block_size;



	amdgpu_vm_set_fragment_size(adev, fragment_size_default);



	DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",

		adev->vm_manager.vm_size, adev->vm_manager.block_size,

	DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",

		 vm_size, adev->vm_manager.block_size,

		 adev->vm_manager.fragment_size);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+3 −4
Original line number Diff line number Diff line
@@ -221,7 +221,6 @@ struct amdgpu_vm_manager { 


	uint64_t				max_pfn;

	uint32_t				num_level;

	uint64_t				vm_size;

	uint32_t				block_size;

	uint32_t				fragment_size;

	/* vram base address for page table entry  */
@@ -314,7 +313,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 
		      struct amdgpu_bo_va *bo_va);

void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,

				 uint32_t fragment_size_default);

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

			   uint32_t fragment_size_default);

int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);

bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+0 −1
Original line number Diff line number Diff line
@@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle) 
		return r;



	amdgpu_vm_adjust_size(adev, 64, 9);

	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;



	adev->mc.mc_mask = 0xffffffffffULL;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

+0 −1
Original line number Diff line number Diff line
@@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle) 
	 * Max GPUVM size for cayman and SI is 40 bits.

	 */

	amdgpu_vm_adjust_size(adev, 64, 9);

	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;



	/* Set the internal MC address mask

	 * This is the max address of the GPU's

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

+0 −1
Original line number Diff line number Diff line
@@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle) 
	 * Max GPUVM size for cayman and SI is 40 bits.

	 */

	amdgpu_vm_adjust_size(adev, 64, 9);

	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;



	/* Set the internal MC address mask

	 * This is the max address of the GPU's

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