Commit fdd0dbd8 authored Jun 03, 2015 by Geert Uytterhoeven Committed by Simon Horman Feb 19, 2016

ARM: dts: r8a7793: Add L2 cache-controller node



Add a device node for the L2 cache, and link the CPU node to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

parent 8ffe93a5

arch/arm/boot/dts/r8a7793.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,7 @@
		< 937500 1000000>,
		< 750000 1000000>,
		< 375000 1000000>;
		next-level-cache = <&L2_CA15>;
		};
		};

		@@ -73,6 +74,12 @@
		};
		};

		L2_CA15: cache-controller@0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		};

		gic: interrupt-controller@f1001000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;

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