Commit fda928ac authored by Jan Andersson's avatar Jan Andersson Committed by Greg Kroah-Hartman
Browse files

USB: UHCI: Support big endian GRUSBHC HC 



This patch adds support for big endian GRUSBHC UHCI controllers.
The HCD bus glue will probe the register interface to determine
the endianness of the controller.

Tested on GR-LEON4-ITX board which has a controller with little endian
interface and on custom LEON3 board with a BE controller.

Signed-off-by: default avatarJan Andersson <jan@gaisler.com>
Acked-by: default avatarAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent c936503f

drivers/usb/host/Kconfig

+4 −2
Original line number Diff line number Diff line
@@ -418,11 +418,13 @@ config USB_UHCI_SUPPORT_NON_PCI_HC 


config USB_UHCI_BIG_ENDIAN_MMIO

	bool

	depends on USB_UHCI_SUPPORT_NON_PCI_HC

	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON

	default y



config USB_UHCI_BIG_ENDIAN_DESC

	bool

	depends on USB_UHCI_SUPPORT_NON_PCI_HC

	depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON

	default y



config USB_FHCI_HCD

	tristate "Freescale QE USB Host Controller support"

drivers/usb/host/uhci-grlib.c

+14 −0
Original line number Diff line number Diff line
@@ -25,6 +25,20 @@ static int uhci_grlib_init(struct usb_hcd *hcd) 
{

	struct uhci_hcd *uhci = hcd_to_uhci(hcd);



	/*

	 * Probe to determine the endianness of the controller.

	 * We know that bit 7 of the PORTSC1 register is always set

	 * and bit 15 is always clear.  If uhci_readw() yields a value

	 * with bit 7 (0x80) turned on then the current little-endian

	 * setting is correct.  Otherwise we assume the value was

	 * byte-swapped; hence the register interface and presumably

	 * also the descriptors are big-endian.

	 */

	if (!(uhci_readw(uhci, USBPORTSC1) & 0x80)) {

		uhci->big_endian_mmio = 1;

		uhci->big_endian_desc = 1;

	}



	uhci->rh_numports = uhci_count_ports(hcd);



	/* Set up pointers to to generic functions */

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