Commit fd91e03e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.6-next-soc' of... 

Merge tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/soc

pmic wrapper:
- add support for MT6779 SoC

cmdq-helper:
- set knows_txdone in mailbox client

* tag 'v5.6-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: pwrap: add support for MT6359 PMIC
  soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs
  dt-bindings: pwrap: mediatek: add pwrap support for MT6779
  soc: mediatek: knows_txdone needs to be set in Mediatek CMDQ helper

Link: https://lore.kernel.org/r/61165e91-f211-ad37-a81c-cbf3ff69fa1b@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a4b58e00 2faccb56

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ Required properties in pwrap device node. 
- compatible:

	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs

	"mediatek,mt6765-pwrap" for MT6765 SoCs

	"mediatek,mt6779-pwrap" for MT6779 SoCs

	"mediatek,mt6797-pwrap" for MT6797 SoCs

	"mediatek,mt7622-pwrap" for MT7622 SoCs

	"mediatek,mt8135-pwrap" for MT8135 SoCs

drivers/soc/mediatek/mtk-cmdq-helper.c

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout) 
	client->pkt_cnt = 0;

	client->client.dev = dev;

	client->client.tx_block = false;

	client->client.knows_txdone = true;

	client->chan = mbox_request_channel(&client->client, index);



	if (IS_ERR(client->chan)) {

drivers/soc/mediatek/mtk-pmic-wrap.c

+128 −0
Original line number Diff line number Diff line
@@ -111,6 +111,28 @@ enum dew_regs { 
	PWRAP_RG_SPI_CON13,

	PWRAP_SPISLV_KEY,



	/* MT6359 only regs */

	PWRAP_DEW_CRC_SWRST,

	PWRAP_DEW_RG_EN_RECORD,

	PWRAP_DEW_RECORD_CMD0,

	PWRAP_DEW_RECORD_CMD1,

	PWRAP_DEW_RECORD_CMD2,

	PWRAP_DEW_RECORD_CMD3,

	PWRAP_DEW_RECORD_CMD4,

	PWRAP_DEW_RECORD_CMD5,

	PWRAP_DEW_RECORD_WDATA0,

	PWRAP_DEW_RECORD_WDATA1,

	PWRAP_DEW_RECORD_WDATA2,

	PWRAP_DEW_RECORD_WDATA3,

	PWRAP_DEW_RECORD_WDATA4,

	PWRAP_DEW_RECORD_WDATA5,

	PWRAP_DEW_RG_ADDR_TARGET,

	PWRAP_DEW_RG_ADDR_MASK,

	PWRAP_DEW_RG_WDATA_TARGET,

	PWRAP_DEW_RG_WDATA_MASK,

	PWRAP_DEW_RG_SPI_RECORD_CLR,

	PWRAP_DEW_RG_CMD_ALERT_CLR,



	/* MT6397 only regs */

	PWRAP_DEW_EVENT_OUT_EN,

	PWRAP_DEW_EVENT_SRC_EN,
@@ -197,6 +219,42 @@ static const u32 mt6358_regs[] = { 
	[PWRAP_SPISLV_KEY] =		0x044a,

};



static const u32 mt6359_regs[] = {

	[PWRAP_DEW_RG_EN_RECORD] =	0x040a,

	[PWRAP_DEW_DIO_EN] =		0x040c,

	[PWRAP_DEW_READ_TEST] =		0x040e,

	[PWRAP_DEW_WRITE_TEST] =	0x0410,

	[PWRAP_DEW_CRC_SWRST] =		0x0412,

	[PWRAP_DEW_CRC_EN] =		0x0414,

	[PWRAP_DEW_CRC_VAL] =		0x0416,

	[PWRAP_DEW_CIPHER_KEY_SEL] =	0x0418,

	[PWRAP_DEW_CIPHER_IV_SEL] =	0x041a,

	[PWRAP_DEW_CIPHER_EN] =		0x041c,

	[PWRAP_DEW_CIPHER_RDY] =	0x041e,

	[PWRAP_DEW_CIPHER_MODE] =	0x0420,

	[PWRAP_DEW_CIPHER_SWRST] =	0x0422,

	[PWRAP_DEW_RDDMY_NO] =		0x0424,

	[PWRAP_DEW_RECORD_CMD0] =	0x0428,

	[PWRAP_DEW_RECORD_CMD1] =	0x042a,

	[PWRAP_DEW_RECORD_CMD2] =	0x042c,

	[PWRAP_DEW_RECORD_CMD3] =	0x042e,

	[PWRAP_DEW_RECORD_CMD4] =	0x0430,

	[PWRAP_DEW_RECORD_CMD5] =	0x0432,

	[PWRAP_DEW_RECORD_WDATA0] =	0x0434,

	[PWRAP_DEW_RECORD_WDATA1] =	0x0436,

	[PWRAP_DEW_RECORD_WDATA2] =	0x0438,

	[PWRAP_DEW_RECORD_WDATA3] =	0x043a,

	[PWRAP_DEW_RECORD_WDATA4] =	0x043c,

	[PWRAP_DEW_RECORD_WDATA5] =	0x043e,

	[PWRAP_DEW_RG_ADDR_TARGET] =	0x0440,

	[PWRAP_DEW_RG_ADDR_MASK] =	0x0442,

	[PWRAP_DEW_RG_WDATA_TARGET] =	0x0444,

	[PWRAP_DEW_RG_WDATA_MASK] =	0x0446,

	[PWRAP_DEW_RG_SPI_RECORD_CLR] =	0x0448,

	[PWRAP_DEW_RG_CMD_ALERT_CLR] =	0x0448,

	[PWRAP_SPISLV_KEY] =		0x044a,

};



static const u32 mt6397_regs[] = {

	[PWRAP_DEW_BASE] =		0xbc00,

	[PWRAP_DEW_EVENT_OUT_EN] =	0xbc00,
@@ -497,6 +555,45 @@ static int mt6765_regs[] = { 
	[PWRAP_DCM_DBC_PRD] =		0x1E0,

};



static int mt6779_regs[] = {

	[PWRAP_MUX_SEL] =		0x0,

	[PWRAP_WRAP_EN] =		0x4,

	[PWRAP_DIO_EN] =		0x8,

	[PWRAP_RDDMY] =			0x20,

	[PWRAP_CSHEXT_WRITE] =		0x24,

	[PWRAP_CSHEXT_READ] =		0x28,

	[PWRAP_CSLEXT_WRITE] =		0x2C,

	[PWRAP_CSLEXT_READ] =		0x30,

	[PWRAP_EXT_CK_WRITE] =		0x34,

	[PWRAP_STAUPD_CTRL] =		0x3C,

	[PWRAP_STAUPD_GRPEN] =		0x40,

	[PWRAP_EINT_STA0_ADR] =		0x44,

	[PWRAP_HARB_HPRIO] =		0x68,

	[PWRAP_HIPRIO_ARB_EN] =		0x6C,

	[PWRAP_MAN_EN] =		0x7C,

	[PWRAP_MAN_CMD] =		0x80,

	[PWRAP_WACS0_EN] =		0x8C,

	[PWRAP_INIT_DONE0] =		0x90,

	[PWRAP_WACS1_EN] =		0x94,

	[PWRAP_WACS2_EN] =		0x9C,

	[PWRAP_INIT_DONE1] =		0x98,

	[PWRAP_INIT_DONE2] =		0xA0,

	[PWRAP_INT_EN] =		0xBC,

	[PWRAP_INT_FLG_RAW] =		0xC0,

	[PWRAP_INT_FLG] =		0xC4,

	[PWRAP_INT_CLR] =		0xC8,

	[PWRAP_INT1_EN] =		0xCC,

	[PWRAP_INT1_FLG] =		0xD4,

	[PWRAP_INT1_CLR] =		0xD8,

	[PWRAP_TIMER_EN] =		0xF0,

	[PWRAP_WDT_UNIT] =		0xF8,

	[PWRAP_WDT_SRC_EN] =		0xFC,

	[PWRAP_WDT_SRC_EN_1] =		0x100,

	[PWRAP_WACS2_CMD] =		0xC20,

	[PWRAP_WACS2_RDATA] =		0xC24,

	[PWRAP_WACS2_VLDCLR] =		0xC28,

};



static int mt6797_regs[] = {

	[PWRAP_MUX_SEL] =		0x0,

	[PWRAP_WRAP_EN] =		0x4,
@@ -938,6 +1035,7 @@ enum pmic_type { 
	PMIC_MT6351,

	PMIC_MT6357,

	PMIC_MT6358,

	PMIC_MT6359,

	PMIC_MT6380,

	PMIC_MT6397,

};
@@ -945,6 +1043,7 @@ enum pmic_type { 
enum pwrap_type {

	PWRAP_MT2701,

	PWRAP_MT6765,

	PWRAP_MT6779,

	PWRAP_MT6797,

	PWRAP_MT7622,

	PWRAP_MT8135,
@@ -1377,6 +1476,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) 
		break;

	case PWRAP_MT2701:

	case PWRAP_MT6765:

	case PWRAP_MT6779:

	case PWRAP_MT6797:

	case PWRAP_MT8173:

	case PWRAP_MT8516:
@@ -1711,6 +1811,15 @@ static const struct pwrap_slv_type pmic_mt6358 = { 
	.pwrap_write = pwrap_write16,

};



static const struct pwrap_slv_type pmic_mt6359 = {

	.dew_regs = mt6359_regs,

	.type = PMIC_MT6359,

	.regmap = &pwrap_regmap_config16,

	.caps = PWRAP_SLV_CAP_DUALIO,

	.pwrap_read = pwrap_read16,

	.pwrap_write = pwrap_write16,

};



static const struct pwrap_slv_type pmic_mt6380 = {

	.dew_regs = NULL,

	.type = PMIC_MT6380,
@@ -1743,6 +1852,9 @@ static const struct of_device_id of_slave_match_tbl[] = { 
	}, {

		.compatible = "mediatek,mt6358",

		.data = &pmic_mt6358,

	}, {

		.compatible = "mediatek,mt6359",

		.data = &pmic_mt6359,

	}, {

		/* The MT6380 PMIC only implements a regulator, so we bind it

		 * directly instead of using a MFD.
@@ -1783,6 +1895,19 @@ static const struct pmic_wrapper_type pwrap_mt6765 = { 
	.init_soc_specific = NULL,

};



static const struct pmic_wrapper_type pwrap_mt6779 = {

	.regs = mt6779_regs,

	.type = PWRAP_MT6779,

	.arb_en_all = 0xfbb7f,

	.int_en_all = 0xfffffffe,

	.int1_en_all = 0,

	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,

	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,

	.caps = 0,

	.init_reg_clock = pwrap_common_init_reg_clock,

	.init_soc_specific = NULL,

};



static const struct pmic_wrapper_type pwrap_mt6797 = {

	.regs = mt6797_regs,

	.type = PWRAP_MT6797,
@@ -1867,6 +1992,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { 
	}, {

		.compatible = "mediatek,mt6765-pwrap",

		.data = &pwrap_mt6765,

	}, {

		.compatible = "mediatek,mt6779-pwrap",

		.data = &pwrap_mt6779,

	}, {

		.compatible = "mediatek,mt6797-pwrap",

		.data = &pwrap_mt6797,

CRA Git | Maintained and supported by SUSTech CRA and CCSE