Commit fd454997 authored by Olof Johansson's avatar Olof Johansson Committed by Grant Likely
Browse files

gpio: samsung: refactor gpiolib init for exynos4/5 



Only code move, no functional change.

Main reason to do this was to get rid of the warnings:

drivers/gpio/gpio-samsung.c: In function 'samsung_gpiolib_init':
drivers/gpio/gpio-samsung.c:2974:1: warning: label 'err_ioremap4' defined but not used [-Wunused-label]
drivers/gpio/gpio-samsung.c:2722:47: warning: unused variable 'gpio_base4' [-Wunused-variable]

without adding more ifdef mess.

I think this whole file would do well being coverted over to a platform
driver and moving most of the tables out to SoC code and/or device trees,
but since that changes init ordering it needs to be done with some care,
i.e. not at this time.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent c8f925b6

drivers/gpio/gpio-samsung.c

+215 −188
Original line number Diff line number Diff line
@@ -2714,78 +2714,13 @@ static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, 
}

#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */



/* TODO: cleanup soc_is_* */

static __init int samsung_gpiolib_init(void)

static __init void exynos4_gpiolib_init(void)

{

#ifdef CONFIG_CPU_EXYNOS4210

	struct samsung_gpio_chip *chip;

	int i, nr_chips;

	void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;

	void __iomem *gpio_base1, *gpio_base2, *gpio_base3;

	int group = 0;



	samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));



	if (soc_is_s3c24xx()) {

		s3c24xx_gpiolib_add_chips(s3c24xx_gpios,

				ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);

	} else if (soc_is_s3c64xx()) {

		samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,

				ARRAY_SIZE(s3c64xx_gpios_2bit),

				S3C64XX_VA_GPIO + 0xE0, 0x20);

		samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,

				ARRAY_SIZE(s3c64xx_gpios_4bit),

				S3C64XX_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,

				ARRAY_SIZE(s3c64xx_gpios_4bit2));

	} else if (soc_is_s5p6440()) {

		samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,

				ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);

		samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,

				ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,

				ARRAY_SIZE(s5p6440_gpios_4bit2));

		s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,

				ARRAY_SIZE(s5p6440_gpios_rbank));

	} else if (soc_is_s5p6450()) {

		samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,

				ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);

		samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,

				ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,

				ARRAY_SIZE(s5p6450_gpios_4bit2));

		s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,

				ARRAY_SIZE(s5p6450_gpios_rbank));

	} else if (soc_is_s5pc100()) {

		group = 0;

		chip = s5pc100_gpios_4bit;

		nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);



		for (i = 0; i < nr_chips; i++, chip++) {

			if (!chip->config) {

				chip->config = &samsung_gpio_cfgs[3];

				chip->group = group++;

			}

		}

		samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);

#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)

		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);

#endif

	} else if (soc_is_s5pv210()) {

		group = 0;

		chip = s5pv210_gpios_4bit;

		nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);



		for (i = 0; i < nr_chips; i++, chip++) {

			if (!chip->config) {

				chip->config = &samsung_gpio_cfgs[3];

				chip->group = group++;

			}

		}

		samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);

#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)

		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);

#endif

	} else if (soc_is_exynos4210()) {

#ifdef CONFIG_CPU_EXYNOS4210

	void __iomem *gpx_base;



	/* gpio part1 */
@@ -2862,9 +2797,24 @@ static __init int samsung_gpiolib_init(void) 
	s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);

#endif



	return;



err_ioremap3:

	iounmap(gpio_base2);

err_ioremap2:

	iounmap(gpio_base1);

err_ioremap1:

	return;

#endif	/* CONFIG_CPU_EXYNOS4210 */

	} else if (soc_is_exynos5250()) {

}



static __init void exynos5_gpiolib_init(void)

{

#ifdef CONFIG_SOC_EXYNOS5250

	struct samsung_gpio_chip *chip;

	int i, nr_chips;

	void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;

	int group = 0;

	void __iomem *gpx_base;



	/* gpio part1 */
@@ -2963,13 +2913,7 @@ static __init int samsung_gpiolib_init(void) 
	}

	samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,

				       nr_chips, gpio_base4);

#endif	/* CONFIG_SOC_EXYNOS5250 */

	} else {

		WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");

		return -ENODEV;

	}



	return 0;

	return;



err_ioremap4:

	iounmap(gpio_base3);
@@ -2978,7 +2922,90 @@ err_ioremap3: 
err_ioremap2:

	iounmap(gpio_base1);

err_ioremap1:

	return -ENOMEM;

	return;



#endif	/* CONFIG_SOC_EXYNOS5250 */

}



/* TODO: cleanup soc_is_* */

static __init int samsung_gpiolib_init(void)

{

	struct samsung_gpio_chip *chip;

	int i, nr_chips;

	int group = 0;



	samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));



	if (soc_is_s3c24xx()) {

		s3c24xx_gpiolib_add_chips(s3c24xx_gpios,

				ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);

	} else if (soc_is_s3c64xx()) {

		samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,

				ARRAY_SIZE(s3c64xx_gpios_2bit),

				S3C64XX_VA_GPIO + 0xE0, 0x20);

		samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,

				ARRAY_SIZE(s3c64xx_gpios_4bit),

				S3C64XX_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,

				ARRAY_SIZE(s3c64xx_gpios_4bit2));

	} else if (soc_is_s5p6440()) {

		samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,

				ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);

		samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,

				ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,

				ARRAY_SIZE(s5p6440_gpios_4bit2));

		s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,

				ARRAY_SIZE(s5p6440_gpios_rbank));

	} else if (soc_is_s5p6450()) {

		samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,

				ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);

		samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,

				ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);

		samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,

				ARRAY_SIZE(s5p6450_gpios_4bit2));

		s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,

				ARRAY_SIZE(s5p6450_gpios_rbank));

	} else if (soc_is_s5pc100()) {

		group = 0;

		chip = s5pc100_gpios_4bit;

		nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);



		for (i = 0; i < nr_chips; i++, chip++) {

			if (!chip->config) {

				chip->config = &samsung_gpio_cfgs[3];

				chip->group = group++;

			}

		}

		samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);

#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)

		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);

#endif

	} else if (soc_is_s5pv210()) {

		group = 0;

		chip = s5pv210_gpios_4bit;

		nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);



		for (i = 0; i < nr_chips; i++, chip++) {

			if (!chip->config) {

				chip->config = &samsung_gpio_cfgs[3];

				chip->group = group++;

			}

		}

		samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);

#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)

		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);

#endif

	} else if (soc_is_exynos4210()) {

		exynos4_gpiolib_init();

	} else if (soc_is_exynos5250()) {

		exynos5_gpiolib_init();

	} else {

		WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");

		return -ENODEV;

	}



	return 0;

}

core_initcall(samsung_gpiolib_init);

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